parent
edd2e9fe0b
commit
996a5f59fb
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@ -1,5 +1,5 @@
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/* Output routines for GCC for ARM/RISCiX.
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Copyright (C) 1991, 1993 Free Software Foundation, Inc.
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Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
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Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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and Martin Simmons (@harleqn.co.uk).
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More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
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@ -443,8 +443,7 @@ shift_operator (x, mode)
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if (code == MULT)
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return power_of_two_operand (XEXP (x, 1));
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return (code == ASHIFT || code == LSHIFT
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|| code == ASHIFTRT || code == LSHIFTRT);
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return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT);
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}
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} /* shift_operator */
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@ -1344,9 +1343,6 @@ shift_instr (op, shift_ptr)
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case ASHIFT:
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mnem = "asl";
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break;
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case LSHIFT:
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mnem = "lsl";
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break;
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case ASHIFTRT:
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mnem = "asr";
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max_shift = 32;
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@ -1,5 +1,5 @@
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/* Definitions of target machine for GNU compiler, for Acorn RISC Machine.
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Copyright (C) 1991, 1993 Free Software Foundation, Inc.
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Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
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Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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and Martin Simmons (@harleqn.co.uk).
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More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
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@ -998,7 +998,7 @@ do \
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goto LABEL; \
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} \
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if (GET_MODE_SIZE (MODE) <= 4 \
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&& (code == LSHIFTRT || code == ASHIFTRT || code == LSHIFT \
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&& (code == LSHIFTRT || code == ASHIFTRT \
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|| code == ASHIFT || code == ROTATERT)) \
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{ \
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rtx op = XEXP (INDEX, 1); \
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@ -1239,7 +1239,6 @@ do \
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&& exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
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return rtx_cost (XEXP (X, 0), GET_CODE (X))+1; \
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return COSTS_N_INSNS (9); \
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case LSHIFT: \
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case ASHIFT: \
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case LSHIFTRT: \
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case ASHIFTRT: \
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@ -1256,8 +1255,7 @@ do \
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return COSTS_N_INSNS (1); \
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break; \
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} \
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else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \
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|| code == LSHIFTRT) \
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else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
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return COSTS_N_INSNS (1); \
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} /* fall through */ \
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case PLUS: \
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@ -1275,8 +1273,7 @@ do \
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return COSTS_N_INSNS (12); \
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break; \
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} \
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else if (code == ASHIFT || code == LSHIFT || code == ASHIFTRT \
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|| code == LSHIFTRT) \
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else if (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT) \
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return COSTS_N_INSNS (1); \
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break; \
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} \
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@ -1342,7 +1339,7 @@ do \
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|| GET_CODE (X) == AND || GET_CODE (X) == IOR \
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|| GET_CODE (X) == XOR || GET_CODE (X) == MULT \
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|| GET_CODE (X) == NOT || GET_CODE (X) == NEG \
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|| GET_CODE (X) == LSHIFT || GET_CODE (X) == LSHIFTRT \
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|| GET_CODE (X) == LSHIFTRT \
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|| GET_CODE (X) == ASHIFT || GET_CODE (X) == ASHIFTRT \
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|| GET_CODE (X) == ROTATERT || GET_CODE (X) == ZERO_EXTRACT) \
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? CC_NOOVmode \
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@ -1367,7 +1364,7 @@ extern int arm_compare_fp;
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{"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
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{"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
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{"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
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{"shift_operator", {ASHIFT, LSHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
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{"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, MULT}}, \
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{"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
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{"load_multiple_operation", {PARALLEL}}, \
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{"store_multiple_operation", {PARALLEL}}, \
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@ -1780,7 +1777,6 @@ do { char dstr[30]; \
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case ASHIFTRT: \
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case LSHIFTRT: \
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case ASHIFT: \
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case LSHIFT: \
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case ROTATERT: \
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{ \
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char *shift_type = shift_instr (GET_CODE (index), \
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@ -1,5 +1,5 @@
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;;- Machine description Acorn RISC Machine for GNU compiler
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;; Copyright (C) 1991, 1993 Free Software Foundation, Inc.
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;; Copyright (C) 1991, 1993, 1994 Free Software Foundation, Inc.
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;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
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;; and Martin Simmons (@harleqn.co.uk).
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;; More major hacks by Richard Earnshaw (rwe11@cl.cam.ac.uk)
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@ -1472,18 +1472,6 @@
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return (output_shifted_move (ASHIFTRT, operands));
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")
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;; lshlsi3 is not defined because shift counts cannot be negative
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;; An unnamed pattern is needed for expansion of zero_extend.
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(define_insn ""
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(lshift:SI (match_operand:SI 1 "s_register_operand" "r")
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(match_operand:SI 2 "arm_rhs_operand" "rn")))]
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""
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"*
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return (output_shifted_move (LSHIFT, operands));
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")
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "s_register_operand" "=r")
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(lshiftrt:SI (match_operand:SI 1 "s_register_operand" "r")
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@ -1,6 +1,5 @@
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/* Definitions of target machine for GNU compiler. Clipper version.
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Copyright (C) 1987, 1988, 1991, 1993 Free Software Foundation, Inc.
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Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
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Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
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This file is part of GNU CC.
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@ -879,7 +878,6 @@ do \
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case MOD: \
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case UMOD: \
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return COSTS_N_INSNS (40); \
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case LSHIFT: \
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case ASHIFT: \
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case LSHIFTRT: \
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case ASHIFTRT: \
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@ -1,6 +1,5 @@
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;;- Machine description for GNU compiler, Clipper Version
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;; Copyright (C) 1987, 1988, 1991, 1993 Free Software Foundation, Inc.
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;; Copyright (C) 1987, 1988, 1991, 1993, 1994 Free Software Foundation, Inc.
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;; Contributed by Holger Teutsch (holger@hotbso.rhein-main.de)
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;; This file is part of GNU CC.
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@ -1129,25 +1128,6 @@
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"shlw %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "lshldi3"
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[(set (match_operand:DI 0 "int_reg_operand" "=r,r")
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(lshift:DI (match_operand:DI 1 "int_reg_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n")))]
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""
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"@
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shll %2,%0
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shlli %2,%0"
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[(set_attr "type" "arith")])
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(define_insn "lshlsi3"
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[(set (match_operand:SI 0 "int_reg_operand" "=r,r")
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(lshift:SI (match_operand:SI 1 "int_reg_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "r,n")))]
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""
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"@
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shlw %2,%0
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shli %2,%0"
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[(set_attr "type" "arith")])
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;;
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;; rotate insn
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@ -1119,7 +1119,6 @@ enum reg_class {
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else break; \
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case MULT: \
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return 4 * (char) (0x03060403 >> target_cpu * 8); \
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case LSHIFT: \
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case ASHIFT: \
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case LSHIFTRT: \
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case ASHIFTRT: \
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@ -1,6 +1,5 @@
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;;- Machine description for GNU compiler
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;;- Convex Version
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;; Copyright (C) 1988, 1993 Free Software Foundation, Inc.
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;;- Machine description for GNU compiler, Convex Version
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;; Copyright (C) 1988, 1993, 1994 Free Software Foundation, Inc.
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;; This file is part of GNU CC.
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@ -1040,81 +1039,6 @@
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;; SImode
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;; Logical left 1, 1 cycle on all machines via add
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(lshift:SI (match_operand:SI 1 "register_operand" "0")
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(const_int 1)))]
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""
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"add.w %0,%0")
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;; C34 general shift is 1 cycle
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d,a")
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(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
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"TARGET_C34"
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"@
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shf.w %2,%0
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shf %2,%0"
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[(set_attr "type" "shfw,shfw")])
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;; else shift left 0..7 is 1 cycle if we use an A register
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=a,?d")
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(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "immediate_operand" "ai,di")))]
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"TARGET_C1 && INTVAL (operands[2]) < (unsigned) 8"
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"@
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shf %2,%0
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shf %2,%0"
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[(set_attr "type" "alu,shfl")])
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=a,?d")
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(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "immediate_operand" "ai,di")))]
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"INTVAL (operands[2]) < (unsigned) 8"
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"@
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shf %2,%0
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shf.w %2,%0"
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[(set_attr "type" "alu,shfw")])
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;; else general left shift
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=d,a")
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(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
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"TARGET_C1"
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"@
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shf %2,%0
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shf %2,%0"
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[(set_attr "type" "shfl,shfw")])
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;; (but C2 shift left by a constant can is faster via multiply)
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(define_insn ""
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[(set (match_operand:SI 0 "register_operand" "=r")
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(lshift:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "const_int_operand" "i")))]
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"TARGET_C2 && INTVAL (operands[2]) < (unsigned) 32"
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"mul.w %z2,%0"
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[(set_attr "type" "mulw")])
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(define_insn "lshlsi3"
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[(set (match_operand:SI 0 "register_operand" "=d,a")
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(lshift:SI (match_operand:SI 1 "register_operand" "0,0")
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(match_operand:SI 2 "nonmemory_operand" "di,ai")))]
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""
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"@
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shf.w %2,%0
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shf %2,%0"
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[(set_attr "type" "shfw,shfw")])
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;; Arithmetic left 1, 1 cycle on all machines via add
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(define_insn ""
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@ -1276,25 +1200,6 @@
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[(set_attr "type" "shfl")])
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;; DImode
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;; Logical left, 1-cycle
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=d")
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(lshift:DI (match_operand:DI 1 "register_operand" "0")
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(const_int 1)))]
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""
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"add.l %0,%0")
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;; Logical left, general
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(define_insn "lshldi3"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(lshift:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:SI 2 "nonmemory_operand" "di")))]
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""
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"shf %2,%0"
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[(set_attr "type" "shfl")])
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;; Arithmetic left, 1-cycle
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(define_insn ""
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@ -1,7 +1,6 @@
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;;- Machine description for GNU compiler
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;;- Elxsi Version
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;; Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
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;; This port done by Mike Stump <mrs@cygnus.com> in 1988, and is the first
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;;- Machine description for GNU compiler, Elxsi Version
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;; Copyright (C) 1987, 1988, 1992, 1994 Free Software Foundation, Inc.
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;; Contributed by Mike Stump <mrs@cygnus.com> in 1988, and is the first
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;; 64 bit port of GNU CC.
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;; Based upon the VAX port.
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@ -792,14 +791,6 @@
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")
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(define_insn "lshldi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(lshift:DI (match_operand:DI 1 "register_operand" "r")
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(match_operand:SI 2 "general_operand" "rn")))]
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""
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"sll\\t%0,%1,%2")
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(define_insn "ashrdi3"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
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@ -983,7 +983,7 @@ extern enum reg_class regno_reg_class[];
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switch (GET_CODE (cc_status.value2)) \
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{ case PLUS: case MINUS: case MULT: \
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case DIV: case UDIV: case MOD: case UMOD: case NEG: \
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case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT: \
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case ASHIFT: case ASHIFTRT: case LSHIFTRT: \
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case ROTATE: case ROTATERT: \
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if (GET_MODE (cc_status.value2) != VOIDmode) \
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cc_status.flags |= CC_NO_OVERFLOW; \
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@ -1,5 +1,5 @@
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;;- Machine description for GNU C compiler for Alliant FX systems
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;; Copyright (C) 1989 Free Software Foundation, Inc.
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;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
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;; Adapted from m68k.md by Paul Petersen (petersen@uicsrd.csrd.uiuc.edu)
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;; and Joe Weening (weening@gang-of-four.stanford.edu).
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@ -1584,27 +1584,6 @@
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;; logical shift instructions
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(define_insn "lshlsi3"
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[(set (match_operand:SI 0 "general_operand" "=d")
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(lshift:SI (match_operand:SI 1 "general_operand" "0")
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(match_operand:SI 2 "general_operand" "dI")))]
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""
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"lsl%.l %2,%0")
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(define_insn "lshlhi3"
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[(set (match_operand:HI 0 "general_operand" "=d")
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(lshift:HI (match_operand:HI 1 "general_operand" "0")
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(match_operand:HI 2 "general_operand" "dI")))]
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""
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"lsl%.w %2,%0")
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(define_insn "lshlqi3"
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[(set (match_operand:QI 0 "general_operand" "=d")
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(lshift:QI (match_operand:QI 1 "general_operand" "0")
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(match_operand:QI 2 "general_operand" "dI")))]
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""
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"lsl%.b %2,%0")
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(define_insn "lshrsi3"
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[(set (match_operand:SI 0 "general_operand" "=d")
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(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
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@ -1,8 +1,6 @@
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;;- Machine description for GNU compiler
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;;- Fujitsu Gmicro Version
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;;- Ported by M.Yuhara, Fujitsu Laboratories LTD.
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;;
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;; Copyright (C) 1990 Free Software Foundation, Inc.
|
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;;- Machine description for GNU compiler, Fujitsu Gmicro Version
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;; Copyright (C) 1990, 1994 Free Software Foundation, Inc.
|
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;; Contributed by M.Yuhara, Fujitsu Laboratories LTD.
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;; This file is part of GNU CC.
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|
@ -1858,50 +1856,86 @@
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;; logical shift instructions
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(define_insn "lshlsi3"
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;; Logical right shift on the gmicro works by negating the shift count,
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;; then emitting a right shift with the shift count negated. This means
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;; that all actual shift counts in the RTL will be positive. This
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;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
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;; which isn't valid.
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|
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(define_expand "lshrsi3"
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[(set (match_operand:SI 0 "general_operand" "=g")
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(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
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(match_operand:SI 2 "general_operand" "g")))]
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""
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT)
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operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
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}")
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(define_insn ""
|
||||
[(set (match_operand:SI 0 "general_operand" "=rm")
|
||||
(lshift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "rmi")))]
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"shl.w %n2,%0")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "general_operand" "=rm")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(neg:SI (match_operand:SI 2 "general_operand" "rm"))))]
|
||||
""
|
||||
"shl.w %2,%0")
|
||||
|
||||
(define_insn "lshlhi3"
|
||||
(define_expand "lshrhi3"
|
||||
[(set (match_operand:HI 0 "general_operand" "=g")
|
||||
(lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
|
||||
(match_operand:HI 2 "general_operand" "g")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) != CONST_INT)
|
||||
operands[2] = gen_rtx (NEG, HImode, negate_rtx (HImode, operands[2]));
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "general_operand" "=rm")
|
||||
(lshift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:HI 2 "general_operand" "rmi")))]
|
||||
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:HI 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"shl.h %n2,%0")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:HI 0 "general_operand" "=rm")
|
||||
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(neg:HI (match_operand:HI 2 "general_operand" "rm"))))]
|
||||
""
|
||||
"shl.h %2,%0")
|
||||
|
||||
(define_insn "lshlqi3"
|
||||
(define_expand "lshrqi3"
|
||||
[(set (match_operand:QI 0 "general_operand" "=g")
|
||||
(lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
|
||||
(match_operand:QI 2 "general_operand" "g")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
if (GET_CODE (operands[2]) != CONST_INT)
|
||||
operands[2] = gen_rtx (NEG, QImode, negate_rtx (QImode, operands[2]));
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "general_operand" "=rm")
|
||||
(lshift:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(match_operand:QI 2 "general_operand" "rmi")))]
|
||||
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(match_operand:QI 2 "const_int_operand" "n")))]
|
||||
""
|
||||
"shl.b %n2,%0")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:QI 0 "general_operand" "=rm")
|
||||
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(neg:QI (match_operand:QI 2 "general_operand" "rm"))))]
|
||||
""
|
||||
"shl.b %2,%0")
|
||||
|
||||
;; lshiftrt -> lshift
|
||||
(define_expand "lshrsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=rm")
|
||||
(lshift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "rmi")))]
|
||||
""
|
||||
" { operands[2] = negate_rtx (SImode, operands[2]); }")
|
||||
|
||||
;; lshiftrt -> lshift
|
||||
(define_expand "lshrhi3"
|
||||
[(set (match_operand:HI 0 "general_operand" "=rm")
|
||||
(lshift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:HI 2 "general_operand" "rmi")))]
|
||||
""
|
||||
" { operands[2] = negate_rtx (HImode, operands[2]); }")
|
||||
|
||||
;; lshiftrt -> lshift
|
||||
(define_expand "lshrqi3"
|
||||
[(set (match_operand:QI 0 "general_operand" "=rm")
|
||||
(lshift:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(match_operand:QI 2 "general_operand" "rmi")))]
|
||||
""
|
||||
" { operands[2] = negate_rtx (QImode, operands[2]); }")
|
||||
|
||||
;; rotate instructions
|
||||
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
;;- Machine description for GNU compiler -- System/370 version.
|
||||
;; Copyright (C) 1989, 1993 Free Software Foundation, Inc.
|
||||
;; Copyright (C) 1989, 1993, 1994 Free Software Foundation, Inc.
|
||||
;; Contributed by Jan Stein (jan@cd.chalmers.se).
|
||||
;; Modifed for MVS C/370 by Dave Pitts (pitts@mcdata.com)
|
||||
|
||||
|
@ -3371,24 +3371,6 @@ check_label_emit ();
|
|||
;;- Logical shift instructions.
|
||||
;;
|
||||
|
||||
;
|
||||
; lshldi3 instruction pattern(s).
|
||||
;
|
||||
|
||||
(define_insn "lshldi3"
|
||||
[(set (match_operand:DI 0 "general_operand" "=d")
|
||||
(lshift:DI (match_operand:DI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "Ja")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
check_label_emit ();
|
||||
mvs_check_page (0, 4, 0);
|
||||
if (REG_P (operands[2]))
|
||||
return \"SLDL %0,0(%2)\";
|
||||
return \"SLDL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshrdi3 instruction pattern(s).
|
||||
;
|
||||
|
@ -3407,23 +3389,6 @@ check_label_emit ();
|
|||
return \"SRDL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshlsi3 instruction pattern(s).
|
||||
;
|
||||
|
||||
(define_insn "lshlsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=d")
|
||||
(lshift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "Ja")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
check_label_emit ();
|
||||
mvs_check_page (0, 4, 0);
|
||||
if (REG_P (operands[2]))
|
||||
return \"SLL %0,0(%2)\";
|
||||
return \"SLL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshrsi3 instruction pattern(s).
|
||||
|
@ -3443,25 +3408,6 @@ check_label_emit ();
|
|||
return \"SRL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshlhi3 instruction pattern(s).
|
||||
;
|
||||
|
||||
(define_insn "lshlhi3"
|
||||
[(set (match_operand:HI 0 "general_operand" "=d")
|
||||
(lshift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "Ja")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
check_label_emit ();
|
||||
CC_STATUS_INIT;
|
||||
mvs_check_page (0, 4, 0);
|
||||
if (REG_P (operands[2]))
|
||||
return \"SLL %0,0(%2)\";
|
||||
return \"SLL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshrhi3 instruction pattern(s).
|
||||
;
|
||||
|
@ -3484,24 +3430,6 @@ check_label_emit ();
|
|||
return \"N %0,=X'0000FFFF'\;SRL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshlqi3 instruction pattern(s).
|
||||
;
|
||||
|
||||
(define_insn "lshlqi3"
|
||||
[(set (match_operand:QI 0 "general_operand" "=d")
|
||||
(lshift:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "Ja")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
check_label_emit ();
|
||||
mvs_check_page (0, 4, 0);
|
||||
if (REG_P (operands[2]))
|
||||
return \"SLL %0,0(%2)\";
|
||||
return \"SLL %0,%c2\";
|
||||
}")
|
||||
|
||||
;
|
||||
; lshrqi3 instruction pattern(s).
|
||||
;
|
||||
|
|
|
@ -1361,7 +1361,7 @@ notice_update_cc (exp, insn)
|
|||
{
|
||||
case PLUS: case MINUS: case MULT:
|
||||
case DIV: case UDIV: case MOD: case UMOD: case NEG:
|
||||
case ASHIFT: case LSHIFT: case ASHIFTRT: case LSHIFTRT:
|
||||
case ASHIFT: case ASHIFTRT: case LSHIFTRT:
|
||||
case ROTATE: case ROTATERT:
|
||||
if (GET_MODE (cc_status.value2) != VOIDmode)
|
||||
cc_status.flags |= CC_NO_OVERFLOW;
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
/* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
|
||||
Copyright (C) 1987, 1988, 1993, 1994 Free Software Foundation, Inc.
|
||||
|
||||
|
||||
This file is part of GNU CC.
|
||||
|
||||
GNU CC is free software; you can redistribute it and/or modify
|
||||
|
@ -1391,7 +1390,6 @@ __transfer_from_trampoline () \
|
|||
break; \
|
||||
case ASHIFT: \
|
||||
case ASHIFTRT: \
|
||||
case LSHIFT: \
|
||||
case LSHIFTRT: \
|
||||
/* A shift by a big integer takes an extra instruction. */ \
|
||||
if (GET_CODE (XEXP (X, 1)) == CONST_INT \
|
||||
|
|
|
@ -1,5 +1,4 @@
|
|||
;;- Machine description for GNU compiler
|
||||
;;- Motorola 68000 Version
|
||||
;;- Machine description for GNU compiler, Motorola 68000 Version
|
||||
;; Copyright (C) 1987, 1988, 1993, 1994 Free Software Foundation, Inc.
|
||||
|
||||
;; This file is part of GNU CC.
|
||||
|
@ -3552,75 +3551,6 @@
|
|||
|
||||
;; On all 68k models, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshift:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "immediate_operand" "i")))]
|
||||
"(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)"
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
return \"swap %0\;clr%.w %0\";
|
||||
}")
|
||||
|
||||
;; On the 68000, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshift:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "immediate_operand" "i")))]
|
||||
"(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT
|
||||
&& INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
|
||||
"*
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
|
||||
operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
|
||||
return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
|
||||
}")
|
||||
|
||||
(define_insn "lshlsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshift:SI (match_operand:SI 1 "register_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "dI")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
if (operands[2] == const1_rtx)
|
||||
return \"add%.l %0,%0\";
|
||||
return \"lsl%.l %2,%0\";
|
||||
}")
|
||||
|
||||
(define_insn "lshlhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=d")
|
||||
(lshift:HI (match_operand:HI 1 "register_operand" "0")
|
||||
(match_operand:HI 2 "general_operand" "dI")))]
|
||||
""
|
||||
"lsl%.w %2,%0")
|
||||
|
||||
(define_insn ""
|
||||
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
|
||||
(lshift:HI (match_dup 0)
|
||||
(match_operand:HI 1 "general_operand" "dI")))]
|
||||
""
|
||||
"lsl%.w %1,%0")
|
||||
|
||||
(define_insn "lshlqi3"
|
||||
[(set (match_operand:QI 0 "register_operand" "=d")
|
||||
(lshift:QI (match_operand:QI 1 "register_operand" "0")
|
||||
(match_operand:QI 2 "general_operand" "dI")))]
|
||||
""
|
||||
"lsl%.b %2,%0")
|
||||
|
||||
(define_insn ""
|
||||
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
|
||||
(lshift:QI (match_dup 0)
|
||||
(match_operand:QI 1 "general_operand" "dI")))]
|
||||
""
|
||||
"lsl%.b %1,%0")
|
||||
|
||||
;; On all 68k models, this makes faster code in a special case.
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/* Subroutines for insn-output.c for Motorola 88000.
|
||||
Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
|
||||
Copyright (C) 1988, 1989, 1990, 1991, 1994 Free Software Foundation, Inc.
|
||||
Contributed by Michael Tiemann (tiemann@mcc.com)
|
||||
Enhanced by Michael Meissner (meissner@osf.org)
|
||||
Version 2 port by Tom Wood (twood@pets.sps.mot.com)
|
||||
|
@ -3059,12 +3059,6 @@ print_operand_address (file, addr)
|
|||
reg_names[0], reg_names[REGNO (XEXP (addr, 0))]);
|
||||
break;
|
||||
|
||||
case LSHIFT:
|
||||
fprintf (file, "%s,%shi16(", reg_names[0], m88k_pound_sign);
|
||||
output_addr_const (file, XEXP (addr, 0));
|
||||
fputc (')', file);
|
||||
break;
|
||||
|
||||
case CONST_INT:
|
||||
fprintf (file, "%s,%d", reg_names[0], INTVAL (addr));
|
||||
break;
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
;;- Machine description for the Motorola 88000 for GNU C compiler
|
||||
;; Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc.
|
||||
;; Copyright (C) 1988, 89, 90, 91, 93, 1994 Free Software Foundation, Inc.
|
||||
;; Contributed by Michael Tiemann (tiemann@mcc.com)
|
||||
;; Additional changes by Michael Meissner (meissner@osf.org)
|
||||
;; Version 2 port by Tom Wood (twood@pets.sps.mot.com)
|
||||
|
@ -325,8 +325,7 @@
|
|||
;; (tege@sics.se). They've changed since then, so don't complain to him
|
||||
;; if they don't work right.
|
||||
|
||||
;; Regarding shifts, gen_lshlsi3 generates ASHIFT. LSHIFT opcodes are
|
||||
;; not produced and should not normally occur. Also, the gen functions
|
||||
;; Regarding shifts, gen_lshlsi3 generates ASHIFT. The gen functions
|
||||
;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing
|
||||
;; special needs to be done here.
|
||||
|
||||
|
@ -3564,28 +3563,7 @@
|
|||
[(set_attr "type" "bit")])
|
||||
|
||||
;;- logical shift instructions. Logical shift left becomes arithmetic
|
||||
;; shift left. LSHIFT is not normally produced, but is supported.
|
||||
|
||||
(define_expand "lshlsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(lshift:SI (match_operand:SI 1 "register_operand" "")
|
||||
(match_operand:SI 2 "arith32_operand" "")))]
|
||||
""
|
||||
"
|
||||
{
|
||||
emit_insn (gen_ashlsi3 (operands[0], operands[1], operands[2]));
|
||||
DONE;
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r")
|
||||
(lshift:SI (match_operand:SI 1 "register_operand" "r,r")
|
||||
(match_operand:SI 2 "arith5_operand" "r,K")))]
|
||||
""
|
||||
"@
|
||||
mak %0,%1,%2
|
||||
mak %0,%1,0<%2>"
|
||||
[(set_attr "type" "bit")])
|
||||
;; shift left.
|
||||
|
||||
(define_expand "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
|
|
|
@ -1549,27 +1549,6 @@
|
|||
|
||||
;; logical shift instructions
|
||||
|
||||
(define_insn "lshlsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=g")
|
||||
(lshift:SI (match_operand:SI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "rmn")))]
|
||||
""
|
||||
"lshd %2,%0")
|
||||
|
||||
(define_insn "lshlhi3"
|
||||
[(set (match_operand:HI 0 "general_operand" "=g")
|
||||
(lshift:HI (match_operand:HI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "rmn")))]
|
||||
""
|
||||
"lshw %2,%0")
|
||||
|
||||
(define_insn "lshlqi3"
|
||||
[(set (match_operand:QI 0 "general_operand" "=g")
|
||||
(lshift:QI (match_operand:QI 1 "general_operand" "0")
|
||||
(match_operand:SI 2 "general_operand" "rmn")))]
|
||||
""
|
||||
"lshb %2,%0")
|
||||
|
||||
;; Logical right shift on the 32k works by negating the shift count.
|
||||
(define_expand "lshrsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=g")
|
||||
|
|
|
@ -1,4 +1,4 @@
|
|||
;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
|
||||
;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
|
||||
;; Copyright (C) 1990, 1991, 1992, 1993, 1994 Free Software Foundation, Inc.
|
||||
;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
|
||||
|
||||
|
@ -859,14 +859,14 @@
|
|||
(define_insn ""
|
||||
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
|
||||
(udiv:SI
|
||||
(plus:DI (lshift:DI
|
||||
(plus:DI (ashift:DI
|
||||
(zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
|
||||
(const_int 32))
|
||||
(zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
|
||||
(match_operand:SI 3 "gpc_reg_operand" "r")))
|
||||
(set (match_operand:SI 2 "register_operand" "=*q")
|
||||
(umod:SI
|
||||
(plus:DI (lshift:DI
|
||||
(plus:DI (ashift:DI
|
||||
(zero_extend:DI (match_dup 1)) (const_int 32))
|
||||
(zero_extend:DI (match_dup 4)))
|
||||
(match_dup 3)))]
|
||||
|
@ -883,12 +883,12 @@
|
|||
(define_expand "udivmodsi4_normal"
|
||||
[(set (match_dup 4) (const_int 0))
|
||||
(parallel [(set (match_operand:SI 0 "" "")
|
||||
(udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
|
||||
(udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
|
||||
(const_int 32))
|
||||
(zero_extend:DI (match_operand:SI 1 "" "")))
|
||||
(match_operand:SI 2 "" "")))
|
||||
(set (match_operand:SI 3 "" "")
|
||||
(umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
|
||||
(umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
|
||||
(const_int 32))
|
||||
(zero_extend:DI (match_dup 1)))
|
||||
(match_dup 2)))])]
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
;;- Machine description for GNU compiler
|
||||
;;- Tahoe version
|
||||
;; Copyright (C) 1989 Free Software Foundation, Inc.
|
||||
;; Machine description for GNU compiler, Tahoe version
|
||||
;; Copyright (C) 1989, 1994 Free Software Foundation, Inc.
|
||||
|
||||
;; This file is part of GNU CC.
|
||||
|
||||
|
@ -850,42 +849,6 @@
|
|||
|
||||
; shifts are very expensive, try some magic first...
|
||||
|
||||
(define_insn "lshlsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=g")
|
||||
(lshift:SI (match_operand:SI 1 "general_operand" "g")
|
||||
(match_operand:QI 2 "general_operand" "g")))]
|
||||
""
|
||||
"*
|
||||
{
|
||||
if (GET_CODE(operands[2]) == REG)
|
||||
return \"mull3 ___shtab[%2],%1,%0\";
|
||||
/* if (GET_CODE(operands[2]) == REG)
|
||||
if (rtx_equal_p (operands[0], operands[1]))
|
||||
return \"mull2 ___shtab[%2],%1\";
|
||||
else
|
||||
return \"mull3 ___shtab[%2],%1,%0\"; */
|
||||
if (GET_CODE(operands[1]) == REG)
|
||||
{
|
||||
if (operands[2] == const1_rtx)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
return \"movaw 0[%1],%0\";
|
||||
}
|
||||
if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2]) == 2)
|
||||
{
|
||||
CC_STATUS_INIT;
|
||||
return \"moval 0[%1],%0\";
|
||||
}
|
||||
}
|
||||
if (GET_CODE(operands[2]) != CONST_INT || INTVAL(operands[2]) == 1)
|
||||
return \"shll %2,%1,%0\";
|
||||
if (rtx_equal_p (operands[0], operands[1]))
|
||||
return \"mull2 %s2,%1\";
|
||||
else
|
||||
return \"mull3 %s2,%1,%0\";
|
||||
}")
|
||||
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "general_operand" "=g")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
;;- Machine description for GNU compiler
|
||||
;;- AT&T we32000 Version
|
||||
;; Machine description for GNU compiler, AT&T we32000 Version
|
||||
;; Copyright (C) 1991, 1992, 1994 Free Software Foundation, Inc.
|
||||
;; Contributed by John Wehle (john@feith1.uucp)
|
||||
;; Copyright (C) 1991-1992 Free Software Foundation, Inc.
|
||||
|
||||
;; This file is part of GNU CC.
|
||||
|
||||
|
@ -682,13 +681,6 @@
|
|||
|
||||
;; logical shift instructions
|
||||
|
||||
;; (define_insn "lshlsi3"
|
||||
;; [(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
|
||||
;; (lshift:SI (match_operand:SI 1 "general_operand" "mri")
|
||||
;; (match_operand:SI 2 "general_operand" "mri")))]
|
||||
;; ""
|
||||
;; "LLSW3 %2, %1, %0")
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=mr")
|
||||
(lshiftrt:SI (match_operand:SI 1 "general_operand" "mri")
|
||||
|
|
Loading…
Reference in New Issue