Remove unnecessary sparc constraint.
* config/sparc/constraints.md ("U"): Delete. * config/sparc/sparc.md: Use 'r' constraint instead of 'U'. * config/sparc/sync.md: Likewise. From-SVN: r192824
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@ -1,7 +1,13 @@
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2012-10-25 David S. Miller <davem@davemloft.net>
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* config/sparc/constraints.md ("U"): Delete.
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* config/sparc/sparc.md: Use 'r' constraint instead of 'U'.
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* config/sparc/sync.md: Likewise.
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2012-10-25 Lawrence Crowl <crowl@google.com>
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2012-10-25 Lawrence Crowl <crowl@google.com>
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* hash-table.h: Add usage documentation.
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* hash-table.h: Add usage documentation.
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(template struct typed_free_remove): Clarify documentation.
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(template struct typed_free_remove): Clarify documentation.
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Rename template parameter.
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Rename template parameter.
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(struct typed_noop_remove): Likewise.
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(struct typed_noop_remove): Likewise.
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(descriptor concept): Change typedef T to value_type.
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(descriptor concept): Change typedef T to value_type.
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@ -138,15 +138,6 @@
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(match_code "mem")
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(match_code "mem")
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(match_test "memory_ok_for_ldd (op)")))
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(match_test "memory_ok_for_ldd (op)")))
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;; Not needed in 64-bit mode
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(define_constraint "U"
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"Pseudo-register or hard even-numbered integer register"
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(and (match_test "TARGET_ARCH32")
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(match_code "reg")
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(ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER")
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(not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0")))
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(match_test "register_ok_for_ldd (op)")))
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;; Equivalent to 'T' but available in 64-bit mode
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;; Equivalent to 'T' but available in 64-bit mode
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(define_memory_constraint "W"
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(define_memory_constraint "W"
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"Memory reference for 'e' constraint floating-point register"
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"Memory reference for 'e' constraint floating-point register"
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@ -1595,9 +1595,9 @@
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(define_insn "*movdi_insn_sp32"
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(define_insn "*movdi_insn_sp32"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=T,o,T,U,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
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"=T,o,T,r,o,r,r,r,?T,?*f,?*f,?o,?*e,?*e, r,?*f,?*e,?W,b,b")
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(match_operand:DI 1 "input_operand"
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(match_operand:DI 1 "input_operand"
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" J,J,U,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))]
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" J,J,r,T,r,o,i,r,*f, T, o,*f, *e, *e,?*f, r, W,*e,J,P"))]
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"! TARGET_ARCH64
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"! TARGET_ARCH64
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&& (register_operand (operands[0], DImode)
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&& (register_operand (operands[0], DImode)
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|| register_or_zero_operand (operands[1], DImode))"
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|| register_or_zero_operand (operands[1], DImode))"
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@ -2302,8 +2302,8 @@
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})
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})
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(define_insn "*movdf_insn_sp32"
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(define_insn "*movdf_insn_sp32"
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[(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,U,T, f, *r, o,o")
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[(set (match_operand:DF 0 "nonimmediate_operand" "=b,b,e,e,*r, f, e,T,W,r,T, f, *r, o,o")
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(match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,U,o#F,*roF,*rG,f"))]
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(match_operand:DF 1 "input_operand" "G,C,e,e, f,*r,W#F,G,e,T,r,o#F,*roF,*rG,f"))]
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"! TARGET_ARCH64
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"! TARGET_ARCH64
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&& (register_operand (operands[0], DFmode)
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&& (register_operand (operands[0], DFmode)
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|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
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|| register_or_zero_or_all_ones_operand (operands[1], DFmode))"
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@ -2541,8 +2541,8 @@
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})
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})
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(define_insn "*movtf_insn_sp32"
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(define_insn "*movtf_insn_sp32"
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[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,U, r")
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[(set (match_operand:TF 0 "nonimmediate_operand" "=b, e,o, o,r, r")
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(match_operand:TF 1 "input_operand" " G,oe,e,rGU,o,roG"))]
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(match_operand:TF 1 "input_operand" " G,oe,e,rG,o,roG"))]
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"! TARGET_ARCH64
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"! TARGET_ARCH64
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&& (register_operand (operands[0], TFmode)
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&& (register_operand (operands[0], TFmode)
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|| register_or_zero_operand (operands[1], TFmode))"
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|| register_or_zero_operand (operands[1], TFmode))"
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@ -7911,8 +7911,8 @@
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(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
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(set_attr "cpu_feature" "vis,vis,vis,*,*,*,*,*,vis3,vis3,*")])
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(define_insn "*mov<VM64:mode>_insn_sp32"
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(define_insn "*mov<VM64:mode>_insn_sp32"
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[(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,U,T, o,*r")
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[(set (match_operand:VM64 0 "nonimmediate_operand" "=e,e,e,*r, f,e,m,m,r,T, o,*r")
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(match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,U,*r,*r"))]
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(match_operand:VM64 1 "input_operand" "Y,C,e, f,*r,m,e,Y,T,r,*r,*r"))]
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"TARGET_VIS
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"TARGET_VIS
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&& ! TARGET_ARCH64
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&& ! TARGET_ARCH64
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&& (register_operand (operands[0], <VM64:MODE>mode)
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&& (register_operand (operands[0], <VM64:MODE>mode)
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@ -115,7 +115,7 @@
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})
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})
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(define_insn "atomic_loaddi_1"
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(define_insn "atomic_loaddi_1"
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[(set (match_operand:DI 0 "register_operand" "=U,?*f")
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[(set (match_operand:DI 0 "register_operand" "=r,?*f")
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(unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
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(unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")]
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UNSPEC_ATOMIC))]
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UNSPEC_ATOMIC))]
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"!TARGET_ARCH64"
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"!TARGET_ARCH64"
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@ -144,7 +144,7 @@
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(define_insn "atomic_storedi_1"
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(define_insn "atomic_storedi_1"
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[(set (match_operand:DI 0 "memory_operand" "=m,m,m")
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[(set (match_operand:DI 0 "memory_operand" "=m,m,m")
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(unspec:DI
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(unspec:DI
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[(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")]
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[(match_operand:DI 1 "register_or_v9_zero_operand" "J,r,?*f")]
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UNSPEC_ATOMIC))]
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UNSPEC_ATOMIC))]
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"!TARGET_ARCH64"
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"!TARGET_ARCH64"
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"@
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"@
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