From 99abb146fd0923ebda2c7e7681adb18e6798a90c Mon Sep 17 00:00:00 2001
From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Date: Mon, 22 Jun 2020 17:11:19 +0100
Subject: [PATCH] arm: Fix the failing mve scalar shift execution tests.

In GCC testsuite the MVE scalar shift execution tests (mve_scalar_shifts[1-4].c) are failings
because of executing them on target hardware which doesn't support MVE instructions. This patch
restricts those tests to execute only on target hardware that support MVE instructions.

2020-06-22  Srinath Parvathaneni  <srinath.parvathaneni@arm.com>

gcc/
	* doc/sourcebuild.texi (arm_v8_1m_mve_fp_ok): Add item.
	(arm_mve_hw): Likewise.

gcc/testsuite/
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c: Modify.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c: Likewise.
	* gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c: Likewise.
	* lib/target-supports.exp (check_effective_target_arm_mve_hw): Define.
---
 gcc/doc/sourcebuild.texi                       |  9 +++++++++
 .../arm/mve/intrinsics/mve_scalar_shifts1.c    |  2 +-
 .../arm/mve/intrinsics/mve_scalar_shifts2.c    |  2 +-
 .../arm/mve/intrinsics/mve_scalar_shifts3.c    |  2 +-
 .../arm/mve/intrinsics/mve_scalar_shifts4.c    |  2 +-
 gcc/testsuite/lib/target-supports.exp          | 18 ++++++++++++++++++
 6 files changed, 31 insertions(+), 4 deletions(-)

diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index e5554c4666e..a12af822443 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -1925,6 +1925,15 @@ ARM target supports options to generate instructions from ARMv8.1-M with
 the M-Profile Vector Extension (MVE). Some multilibs may be incompatible
 with these options.
 
+@item arm_v8_1m_mve_fp_ok
+ARM target supports options to generate instructions from ARMv8.1-M with
+the Half-precision floating-point instructions (HP), Floating-point Extension
+(FP) along with M-Profile Vector Extension (MVE). Some multilibs may be
+incompatible with these options.
+
+@item arm_mve_hw
+Test system supports executing MVE instructions.
+
 @item arm_v8m_main_cde
 ARM target supports options to generate instructions from ARMv8-M with
 the Custom Datapath Extension (CDE). Some multilibs may be incompatible
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
index e1c136e7f30..db2335fc76e 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts1.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
index 0b5a8edb158..5a63d385cb7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts2.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
index 7e3da54f5e6..f0d5ee32f82 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts3.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
index 8bee12f7fdf..283742fcf98 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_scalar_shifts4.c
@@ -1,5 +1,5 @@
 /* { dg-do run } */
-/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-require-effective-target arm_mve_hw } */
 /* { dg-options "-O2" } */
 /* { dg-add-options arm_v8_1m_mve } */
 
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 862a0735b49..ab0ee32fc91 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4671,6 +4671,24 @@ proc check_effective_target_arm_cmse_ok {} {
     } "-mcmse"];
 }
 
+# Return 1 if the target supports executing MVE instructions, 0
+# otherwise.
+
+proc check_effective_target_arm_mve_hw {} {
+    return [check_runtime arm_mve_hw_available {
+	int
+	main (void)
+	{
+	  long long a = 16;
+	  int b = 3;
+	  asm ("sqrshrl %Q1, %R1, #64, %2"
+	       : "=l" (a)
+	       : "0" (a), "r" (b));
+	  return (a != 2);
+	}
+    } ""]
+}
+
 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
 # clearing instructions (clrm, vscclrm, vstr/vldr with FPCXT) is available.