sparc: Convert to mem_thread_fence.
* config/sparc/predicates.md (zero_or_v7_operand): New.
* config/sparc/sparc.c (sparc_emit_membar_for_model): New.
* config/sparc/sparc-protos.h: Update.
* config/sparc/sync.md (mem_thread_fence): New.
(memory_barrier): Use sparc_emit_membar_for_model.
(membar, *membar_empty, *membar_storestore, *membar_storeload): New.
(*membar_v8): Accept and ignore the membar mask.
(*membar): Accept and print the membar mask.
From-SVN: r181848
This commit is contained in:
Richard Henderson
Richard Henderson
parent
ef5784915f
commit
9a7389088f
@ -1,3 +1,14 @@
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2011-11-30 Richard Henderson <rth@redhat.com>
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* config/sparc/predicates.md (zero_or_v7_operand): New.
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* config/sparc/sparc.c (sparc_emit_membar_for_model): New.
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* config/sparc/sparc-protos.h: Update.
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* config/sparc/sync.md (mem_thread_fence): New.
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(memory_barrier): Use sparc_emit_membar_for_model.
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(membar, *membar_empty, *membar_storestore, *membar_storeload): New.
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(*membar_v8): Accept and ignore the membar mask.
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(*membar): Accept and print the membar mask.
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2011-11-30 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
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* config/arm/arm.c (arm_issue_rate): Cortex-A15 can triple issue.
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@ -111,6 +111,10 @@
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(define_predicate "const_double_or_vector_operand"
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(match_code "const_double,const_vector"))
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;; Return true if OP is Zero, or if the target is V7.
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(define_predicate "zero_or_v7_operand"
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(ior (match_test "op == const0_rtx")
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(match_test "!TARGET_V8 && !TARGET_V9")))
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;; Predicates for symbolic constants.
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@ -113,4 +113,6 @@ unsigned int sparc_regmode_natural_size (enum machine_mode);
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bool sparc_modes_tieable_p (enum machine_mode, enum machine_mode);
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#endif /* RTX_CODE */
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extern void sparc_emit_membar_for_model (enum memmodel, int, int);
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#endif /* __SPARC_PROTOS_H__ */
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@ -10849,6 +10849,53 @@ sparc_mangle_type (const_tree type)
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}
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#endif
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/* Expand a membar instruction for various use cases. Both the LOAD_STORE
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and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
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bit 0 indicates that X is true, and bit 1 indicates Y is true. */
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void
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sparc_emit_membar_for_model (enum memmodel model,
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int load_store, int before_after)
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{
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/* Bits for the MEMBAR mmask field. */
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const int LoadLoad = 1;
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const int StoreLoad = 2;
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const int LoadStore = 4;
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const int StoreStore = 8;
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int mm = 0;
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if (before_after & 1)
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{
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if (model == MEMMODEL_ACQUIRE
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|| model == MEMMODEL_ACQ_REL
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|| model == MEMMODEL_SEQ_CST)
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{
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if (load_store & 1)
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mm |= LoadLoad | LoadStore;
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if (load_store & 2)
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mm |= StoreLoad | StoreStore;
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}
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}
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if (before_after & 2)
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{
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if (model == MEMMODEL_RELEASE
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|| model == MEMMODEL_ACQ_REL
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|| model == MEMMODEL_SEQ_CST)
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{
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if (load_store & 1)
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mm |= LoadLoad | StoreLoad;
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if (load_store & 2)
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mm |= LoadStore | StoreStore;
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}
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}
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/* For raw barriers (before+after), always emit a barrier.
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This will become a compile-time barrier if needed. */
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if (mm || before_after == 3)
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emit_insn (gen_membar (GEN_INT (mm)));
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}
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/* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
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compare and swap on the word containing the byte or half-word. */
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@ -1,5 +1,5 @@
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;; GCC machine description for SPARC synchronization instructions.
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;; Copyright (C) 2005, 2007, 2009, 2010
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;; Copyright (C) 2005, 2007, 2009, 2010, 2011
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;; Free Software Foundation, Inc.
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;;
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;; This file is part of GCC.
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@ -23,36 +23,87 @@
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(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")])
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(define_mode_attr modesuffix [(SI "") (DI "x")])
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(define_expand "memory_barrier"
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[(set (match_dup 0)
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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(define_expand "mem_thread_fence"
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[(match_operand:SI 0 "const_int_operand")]
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"TARGET_V8 || TARGET_V9"
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{
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operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[0]) = 1;
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enum memmodel model = (enum memmodel) INTVAL (operands[0]);
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sparc_emit_membar_for_model (model, 3, 3);
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DONE;
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})
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;; In V8, loads are blocking and ordered wrt earlier loads, i.e. every load
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;; is virtually followed by a load barrier (membar #LoadStore | #LoadLoad).
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;; In PSO, stbar orders the stores (membar #StoreStore).
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;; In TSO, ldstub orders the stores wrt subsequent loads (membar #StoreLoad).
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;; The combination of the three yields a full memory barrier in all cases.
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(define_expand "memory_barrier"
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[(const_int 0)]
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"TARGET_V8 || TARGET_V9"
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{
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sparc_emit_membar_for_model (MEMMODEL_SEQ_CST, 3, 3);
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DONE;
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})
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(define_expand "membar"
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[(set (match_dup 1)
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(unspec:BLK [(match_dup 1)
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(match_operand:SI 0 "const_int_operand")]
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UNSPEC_MEMBAR))]
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"TARGET_V8 || TARGET_V9"
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{
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operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
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MEM_VOLATILE_P (operands[1]) = 1;
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})
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;; A compiler-only memory barrier. Generic code, when checking for the
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;; existance of various named patterns, uses asm("":::"memory") when we
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;; don't need an actual instruction. Here, it's easiest to pretend that
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;; membar 0 is such a barrier. Further, this gives us a nice hook to
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;; ignore all such barriers on Sparc V7.
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(define_insn "*membar_empty"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")]
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UNSPEC_MEMBAR))]
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""
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""
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[(set_attr "type" "multi")
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(set_attr "length" "0")])
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;; For V8, STBAR is exactly membar #StoreStore, by definition.
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(define_insn "*membar_storestore"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))]
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"TARGET_V8"
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"stbar"
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[(set_attr "type" "multi")])
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;; For V8, LDSTUB has the effect of membar #StoreLoad
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(define_insn "*membar_storeload"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))]
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"TARGET_V8"
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"ldstub\t[%%sp-1], %%g0"
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[(set_attr "type" "multi")])
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;; Put the two together, in combination with the fact that V8 implements PSO
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;; as its weakest memory model, means a full barrier. Match all remaining
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;; instances of the membar pattern for Sparc V8.
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(define_insn "*membar_v8"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
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UNSPEC_MEMBAR))]
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"TARGET_V8"
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"stbar\n\tldstub\t[%%sp-1], %%g0"
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[(set_attr "type" "multi")
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(set_attr "length" "2")])
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;; membar #StoreStore | #LoadStore | #StoreLoad | #LoadLoad
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;; For V9, we have the full membar instruction.
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(define_insn "*membar"
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[(set (match_operand:BLK 0 "" "")
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(unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))]
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(unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")]
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UNSPEC_MEMBAR))]
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"TARGET_V9"
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"membar\t15"
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"membar\t%1"
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[(set_attr "type" "multi")])
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;;;;;;;;
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(define_expand "sync_compare_and_swap<mode>"
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[(match_operand:I12MODE 0 "register_operand" "")
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(match_operand:I12MODE 1 "memory_operand" "")
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