alpha.c: Fix comment typos.
* config/alpha/alpha.c: Fix comment typos. * config/alpha/alpha.md: Likewise. * config/arm/arm.c: Likewise. * config/arm/arm.md: Likewise. * config/arm/lib1funcs.asm: Likewise. * config/avr/avr.md: Likewise. * config/arm/README-interworking: Fix typos. From-SVN: r69277
This commit is contained in:
Kazu Hirata
Kazu Hirata
parent
4ed432168c
commit
9a9f7594fd
@ -1,3 +1,13 @@
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2003-07-12 Kazu Hirata <kazu@cs.umass.edu>
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* config/alpha/alpha.c: Fix comment typos.
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* config/alpha/alpha.md: Likewise.
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* config/arm/arm.c: Likewise.
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* config/arm/arm.md: Likewise.
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* config/arm/lib1funcs.asm: Likewise.
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* config/avr/avr.md: Likewise.
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* config/arm/README-interworking: Fix typos.
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2003-07-12 Kazu Hirata <kazu@cs.umass.edu>
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* c-format.c: Fix comment formatting.
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@ -233,7 +233,7 @@ override_options (void)
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flag_pic = 0;
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}
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/* On Unicos/Mk, the native compiler consistenly generates /d suffices for
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/* On Unicos/Mk, the native compiler consistently generates /d suffices for
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floating-point instructions. Make that the default for this target. */
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if (TARGET_ABI_UNICOSMK)
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alpha_fprm = ALPHA_FPRM_DYN;
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@ -3481,7 +3481,7 @@ alpha_split_conditional_move (enum rtx_code code, rtx dest, rtx cond,
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be shared. */
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if (f == 0 && exact_log2 (diff) > 0
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/* On EV6, we've got enough shifters to make non-arithmatic shifts
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/* On EV6, we've got enough shifters to make non-arithmetic shifts
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viable over a longer latency cmove. On EV5, the E0 slot is a
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scarce resource, and on EV4 shift has the same latency as a cmove. */
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&& (diff <= 8 || alpha_cpu == PROCESSOR_EV6))
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@ -5120,7 +5120,7 @@ alpha_use_dfa_pipeline_interface (void)
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For EV4, loads can be issued to either IB0 or IB1, thus we have 2
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alternative schedules. For EV5, we can choose between E0/E1 and
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FA/FM. For EV6, an arithmatic insn can be issued to U0/U1/L0/L1. */
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FA/FM. For EV6, an arithmetic insn can be issued to U0/U1/L0/L1. */
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static int
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alpha_multipass_dfa_lookahead (void)
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@ -120,7 +120,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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;; The ROUND_SUFFIX attribute marks which instructions require a
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;; rounding-mode suffix. The value NONE indicates no suffix,
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;; the value NORMAL indicates a suffix controled by alpha_fprm.
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;; the value NORMAL indicates a suffix controlled by alpha_fprm.
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(define_attr "round_suffix" "none,normal,c"
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(const_string "none"))
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@ -133,7 +133,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none"
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;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
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;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
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;;
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;; The actual suffix emitted is controled by alpha_fptm.
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;; The actual suffix emitted is controlled by alpha_fptm.
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(define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
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(const_string "none"))
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@ -404,7 +404,7 @@ Instead the pseudo op is attached to a new label .real_start_of_<name>
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(where <name> is the name of the function) which indicates the start
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of the Thumb code. This does have the interesting side effect in that
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if this function is now called from a Thumb mode piece of code
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outsside of the current file, the linker will generate a calling stub
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outside of the current file, the linker will generate a calling stub
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to switch from Thumb mode into ARM mode, and then this is immediately
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overridden by the function's header which switches back into Thumb
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mode.
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@ -452,7 +452,7 @@ static const struct processors all_architectures[] =
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{ NULL, 0 }
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};
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/* This is a magic stucture. The 'string' field is magically filled in
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/* This is a magic structure. The 'string' field is magically filled in
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with a pointer to the value specified by the user on the command line
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assuming that the user has specified such a value. */
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@ -10248,7 +10248,7 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
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return VALID_IWMMXT_REG_MODE (mode);
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if (regno <= LAST_ARM_REGNUM)
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/* We allow any value to be stored in the general regisetrs. */
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/* We allow any value to be stored in the general registers. */
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return 1;
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if ( regno == FRAME_POINTER_REGNUM
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@ -11648,7 +11648,7 @@ thumb_far_jump_used_p (int in_prologue)
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&& get_attr_far_jump (insn) == FAR_JUMP_YES
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)
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{
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/* Record the fact that we have decied that
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/* Record the fact that we have decided that
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the function does use far jumps. */
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cfun->machine->far_jump_used = 1;
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return 1;
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@ -75,18 +75,18 @@
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; and stack frame generation. Operand 0 is the
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; register to "use".
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(UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
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(UNSPEC_WSHUFH 8) ; Used by the instrinsic form of the iWMMXt WSHUFH instruction.
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(UNSPEC_WACC 9) ; Used by the instrinsic form of the iWMMXt WACC instruction.
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(UNSPEC_TMOVMSK 10) ; Used by the instrinsic form of the iWMMXt TMOVMSK instruction.
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(UNSPEC_WSAD 11) ; Used by the instrinsic form of the iWMMXt WSAD instruction.
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(UNSPEC_WSADZ 12) ; Used by the instrinsic form of the iWMMXt WSADZ instruction.
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(UNSPEC_WMACS 13) ; Used by the instrinsic form of the iWMMXt WMACS instruction.
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(UNSPEC_WMACU 14) ; Used by the instrinsic form of the iWMMXt WMACU instruction.
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(UNSPEC_WMACSZ 15) ; Used by the instrinsic form of the iWMMXt WMACSZ instruction.
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(UNSPEC_WMACUZ 16) ; Used by the instrinsic form of the iWMMXt WMACUZ instruction.
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(UNSPEC_CLRDI 17) ; Used by the instrinsic form of the iWMMXt CLRDI instruction.
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(UNSPEC_WMADDS 18) ; Used by the instrinsic form of the iWMMXt WMADDS instruction.
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(UNSPEC_WMADDU 19) ; Used by the instrinsic form of the iWMMXt WMADDU instruction.
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(UNSPEC_WSHUFH 8) ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
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(UNSPEC_WACC 9) ; Used by the intrinsic form of the iWMMXt WACC instruction.
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(UNSPEC_TMOVMSK 10) ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
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(UNSPEC_WSAD 11) ; Used by the intrinsic form of the iWMMXt WSAD instruction.
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(UNSPEC_WSADZ 12) ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
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(UNSPEC_WMACS 13) ; Used by the intrinsic form of the iWMMXt WMACS instruction.
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(UNSPEC_WMACU 14) ; Used by the intrinsic form of the iWMMXt WMACU instruction.
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(UNSPEC_WMACSZ 15) ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
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(UNSPEC_WMACUZ 16) ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
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(UNSPEC_CLRDI 17) ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
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(UNSPEC_WMADDS 18) ; Used by the intrinsic form of the iWMMXt WMADDS instruction.
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(UNSPEC_WMADDU 19) ; Used by the intrinsic form of the iWMMXt WMADDU instruction.
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]
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)
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@ -243,7 +243,7 @@
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; Only model the write buffer for ARM6 and ARM7. Earlier processors don't
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; have one. Later ones, such as StrongARM, have write-back caches, so don't
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; suffer blockages enough to warrent modelling this (and it can adversely
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; suffer blockages enough to warrant modelling this (and it can adversely
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; affect the schedule).
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(define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7")))
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@ -5106,7 +5106,7 @@
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;; Compare & branch insns
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;; The range calcualations are based as follows:
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;; The range calculations are based as follows:
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;; For forward branches, the address calculation returns the address of
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;; the next instruction. This is 2 beyond the branch instruction.
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;; For backward branches, the address calculation returns the address of
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@ -165,7 +165,7 @@ lr .req r14
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pc .req r15
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#endif
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/* ------------------------------------------------------------------------ */
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/* Bodies of the divsion and modulo routines. */
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/* Bodies of the division and modulo routines. */
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/* ------------------------------------------------------------------------ */
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.macro ARM_DIV_MOD_BODY modulo
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LSYM(Loop1):
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@ -2255,7 +2255,7 @@
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;; ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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;; This instructin sets Z flag
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;; This instruction sets Z flag
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(define_insn "sez"
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[(set (cc0) (const_int 0))]
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