x86-tune.def: Add documentation for each of the options; add whitespace.
* config/i386/x86-tune.def: Add documentation for each of the options; add whitespace. From-SVN: r203013
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
b0ff06daf8
commit
9ac2f5386c
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@ -1,3 +1,8 @@
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2013-09-28 Jan Hubicka <jh@suse.cz>
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* config/i386/x86-tune.def: Add documentation for each of the options;
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add whitespace.
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2013-09-28 Jan Hubicka <jh@suse.cz>
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* x86-tune.def (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Enable for generic.
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@ -24,207 +24,378 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
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work well with PPro base chips. */
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DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
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m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
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Some chips, like 486 and Pentium have problems with these sequences. */
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DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
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m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
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| m_GENERIC)
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/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
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of mozbl/movwl. */
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DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and", m_486 | m_PENT)
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/* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
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inline strlen. This affects only -minline-all-stringops mode. By
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default we always dispatch to a library since our internal strlen
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is bad. */
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DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen",
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m_486 | m_PENT | m_PPRO | m_ATOM | m_SLM | m_CORE_ALL | m_K6
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| m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
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on simulation result. But after P4 was made, no performance benefit
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was observed with branch hints. It also increases the code size.
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As a result, icc never generates branch hints. */
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DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS, "branch_prediction_hints", 0)
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/* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
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an integer register. */
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DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
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/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
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DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
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| m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
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/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
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partial dependencies. */
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DEF_TUNE (X86_TUNE_MOVX, "movx",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GEODE
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| m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
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register stalls on Generic32 compilation setting as well. However
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in current implementation the partial register stalls are not eliminated
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/* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
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use of partial registers by renaming. This improved performance of 16bit
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code where upper halves of registers are not used. It also leads to
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an penalty whenever a 16bit store is followed by 32bit use. This flag
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disables production of such sequences in common cases.
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See also X86_TUNE_HIMODE_MATH.
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In current implementation the partial register stalls are not eliminated
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very well - they can be introduced via subregs synthesized by combine
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and can happen in caller/callee saving sequences. */
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DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
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/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of of flags
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set by instructions affecting just some flags (in particular shifts).
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This is because Core2 resolves dependencies on whole flags register
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and such sequences introduce false dependency on previous instruction
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setting full flags.
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The flags does not affect generation of INC and DEC that is controlled
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by X86_TUNE_USE_INCDEC.
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This flag may be dropped from generic once core2-corei5 machines are
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rare enough. */
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DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
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m_CORE2 | m_GENERIC)
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/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
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* on 16-bit immediate moves into memory on Core2 and Corei7. */
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on 16-bit immediate moves into memory on Core2 and Corei7. */
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DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC)
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/* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
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integer operand.
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FIXME: Why this is disabled for modern chips? */
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DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
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m_386 | m_486 | m_K6_GEODE)
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/* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
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integer operand. */
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DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
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~(m_PENT | m_PPRO | m_CORE_ALL | m_ATOM
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| m_SLM | m_AMD_MULTIPLE | m_GENERIC))
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/* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
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integer register. */
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DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
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/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
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DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd", ~(m_PENT | m_ATOM | m_SLM | m_K6))
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/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
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DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
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/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
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directly to memory. */
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DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
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/* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
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such as "add $1, mem". */
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DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write", ~m_PENT)
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/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
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as "add mem, reg". */
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DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_PPRO))
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/* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
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corresponding 32bit arithmetic. */
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DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
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m_386 | m_486 | m_PENT | m_CORE_ALL | m_ATOM | m_SLM
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| m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
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into 16bit/8bit when resulting sequence is shorter. For example
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for "and $-65536, reg" to 16bit store of 0. */
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DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix", ~(m_386 | m_486 | m_PENT))
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/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
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as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
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DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
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/* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */
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DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", ~0)
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/* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
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register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
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might be considered for Generic32 if our scheme for avoiding partial
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stalls was more effective. */
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/* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
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On PPro this flag is meant to avoid partial register stalls. */
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DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
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/* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
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arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme
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is usually used for RISC targets. */
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DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", 0)
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/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid
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partial register stalls on PentiumPro targets. */
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DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
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/* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
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over esp addition. */
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DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT | m_PPRO)
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/* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
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over esp addition. */
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DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT)
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/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
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over esp subtraction. */
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DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
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| m_K6_GEODE)
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/* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
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over esp subtraction. */
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DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_K6_GEODE)
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/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
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for DFmode copies */
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DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
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~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM
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| m_GEODE | m_AMD_MULTIPLE | m_GENERIC))
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/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
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on modern chips. Preffer stores affecting whole integer register
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over partial stores. For example preffer MOVZBL or MOVQ to load 8bit
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value over movb. */
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DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
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m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE
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| m_GENERIC)
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
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conflict here in between PPro/Pentium4 based chips that thread 128bit
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SSE registers as single units versus K8 based chips that divide SSE
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registers to two 64bit halves. This knob promotes all store destinations
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to be 128bit to allow register renaming on 128bit SSE units, but usually
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results in one extra microop on 64bit SSE units. Experimental results
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shows that disabling this option on P4 brings over 20% SPECfp regression,
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while enabling it on K8 brings roughly 2.4% regression that can be partly
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masked by careful scheduling of moves. */
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/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
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destinations to be 128bit to allow register renaming on 128bit SSE units,
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but usually results in one extra microop on 64bit SSE units.
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Experimental results shows that disabling this option on P4 brings over 20%
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SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
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that can be partly masked by careful scheduling of moves. */
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DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMDFAM10
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| m_BDVER | m_GENERIC)
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/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
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of a sequence loading registers by parts. */
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DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
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m_COREI7 | m_AMDFAM10 | m_BDVER | m_BTVER | m_SLM | m_GENERIC)
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/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
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of a sequence loading registers by parts. */
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DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
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m_COREI7 | m_BDVER | m_SLM | m_GENERIC)
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/* Use packed single precision instructions where posisble. I.e. movups instead
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of movupd. */
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DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
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m_BDVER)
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/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
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are resolved on SSE register parts instead of whole registers, so we may
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maintain just lower part of scalar values in proper format leaving the
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upper part undefined. */
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DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
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/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.
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FIXME: Shall we enable it for generic? */
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DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
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m_AMD_MULTIPLE | m_CORE_ALL)
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/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
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xorps/xorpd and other variants.
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FIXME: Shall we enable it buldozers and for generic? */
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DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL)
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/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
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full sized loads. */
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DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
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m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
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considered on critical path. */
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DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
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m_PPRO | m_ATHLON_K8)
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/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
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considered on critical path. */
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DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
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m_PPRO | m_ATHLON_K8)
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/* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
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longer "sal $1, reg". */
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DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
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/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
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DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
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/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
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to SSE registers. If disabled, the moves will be done by storing
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the value to memory and reloading. */
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DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
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~(m_AMD_MULTIPLE | m_GENERIC))
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/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
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to integer registers. If disabled, the moves will be done by storing
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the value to memory and reloading. */
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DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
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~m_ATHLON_K8)
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/* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
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to use both SSE and integer registers at a same time.
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FIXME: revisit importance of this for generic. */
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DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
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~(m_AMDFAM10 | m_BDVER ))
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~(m_AMDFAM10 | m_BDVER))
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/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
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than 4 branch instructions in the 16 byte window. */
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DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
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m_PPRO | m_P4_NOCONA | m_ATOM | m_SLM | m_ATHLON_K8 | m_AMDFAM10)
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/* X86_TUNE_SCHEDULE: Enable scheduling. */
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DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
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m_PENT | m_PPRO | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
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| m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
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DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
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m_CORE_ALL | m_ATOM | m_SLM | m_AMD_MULTIPLE | m_GENERIC)
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/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */
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DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
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~(m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_GENERIC))
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/* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
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of conditional jump or directly preceded by other jump instruction.
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This is important for AND K8-AMDFAM10 because the branch prediction
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architecture expect at most one jump per 2 byte window. Failing to
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pad returns leads to misaligned return stack. */
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DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
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m_ATHLON_K8 | m_AMDFAM10 | m_GENERIC)
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/* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
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instructions long. */
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DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_ATOM)
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/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
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DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
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m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
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| m_ATHLON_K8 | m_GENERIC)
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/* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
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forms of instructions on K8 targets. */
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DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
|
||||
m_K8)
|
||||
|
||||
/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
|
||||
and SImode multiply, but 386 and 486 do HImode multiply faster. */
|
||||
DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
|
||||
~(m_386 | m_486))
|
||||
|
||||
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
|
||||
vector path on AMD machines. */
|
||||
vector path on AMD machines.
|
||||
FIXME: Do we need to enable this for core? */
|
||||
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
|
||||
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
|
||||
machines. */
|
||||
machines.
|
||||
FIXME: Do we need to enable this for core? */
|
||||
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
|
||||
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
|
||||
than a MOV. */
|
||||
DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT)
|
||||
|
||||
/* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
|
||||
but one byte longer. */
|
||||
DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT)
|
||||
|
||||
/* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
|
||||
operand that cannot be represented using a modRM byte. The XOR
|
||||
replacement is long decoded, so this split helps here as well. */
|
||||
DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
|
||||
|
||||
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
|
||||
from FP to FP. */
|
||||
from FP to FP. This form of instructions avoids partial write to the
|
||||
destination. */
|
||||
DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
|
||||
m_CORE_ALL | m_AMDFAM10 | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
|
||||
from integer to FP. */
|
||||
DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
|
||||
|
||||
/* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
|
||||
with a subsequent conditional jump instruction into a single
|
||||
compare-and-branch uop. */
|
||||
compare-and-branch uop.
|
||||
FIXME: revisit for generic. */
|
||||
DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH, "fuse_cmp_and_branch", m_BDVER | m_CORE_ALL)
|
||||
|
||||
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
|
||||
will impact LEA instruction selection. */
|
||||
DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_ATOM | m_SLM)
|
||||
|
||||
/* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
|
||||
instructions. */
|
||||
DEF_TUNE (X86_TUNE_VECTORIZE_DOUBLE, "vectorize_double", ~m_ATOM)
|
||||
|
||||
/* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
|
||||
at -O3. For the moment, the prefetching seems badly tuned for Intel
|
||||
chips. */
|
||||
DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
|
||||
m_K6_GEODE | m_AMD_MULTIPLE)
|
||||
|
||||
/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
|
||||
the auto-vectorizer. */
|
||||
DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2)
|
||||
|
||||
/* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
|
||||
during reassociation of integer computation. */
|
||||
DEF_TUNE (X86_TUNE_REASSOC_INT_TO_PARALLEL, "reassoc_int_to_parallel",
|
||||
m_ATOM)
|
||||
|
||||
/* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
|
||||
during reassociation of fp computation. */
|
||||
DEF_TUNE (X86_TUNE_REASSOC_FP_TO_PARALLEL, "reassoc_fp_to_parallel",
|
||||
m_ATOM | m_SLM | m_HASWELL | m_BDVER1 | m_BDVER2 | m_GENERIC)
|
||||
|
||||
/* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
|
||||
regs instead of memory. */
|
||||
DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
|
||||
m_CORE_ALL)
|
||||
|
||||
/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
|
||||
a conditional move. */
|
||||
DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
|
||||
m_ATOM | m_SLM)
|
||||
|
||||
/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
|
||||
fp converts to destination register. */
|
||||
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
|
||||
|
|
|
|||
Loading…
Reference in New Issue