re PR target/29473 (-masm=intel combined with -march=athlon64 has some issues.)
PR target/29473
PR target/29493
* config/i386/i386.c (output_pic_addr_const): Support Intel asm syntax.
(print_reg): Print register prefix only with AT&T asm syntax.
Support pc_rtx for RIP register.
(print_operand_address): Use print_reg()'s pc_rtx support for RIP
relative addressing. Always print segment register prefix with AT&T
asm syntax and never with Intel asm syntax.
(print_operand): Suppress 'XXX PTR' prefix for BLKmode operands.
Fix prefix for 16-byte XFmode operands.
(output_addr_const_extra): Support Intel asm syntax.
(x86_file_start): Don't use register prefix with Intel asm syntax.
* config/i386/i386.md ("*zero_extendqihi2_movzbl"): Fix typo.
("return_internal_long"): Fix Intel asm syntax output.
("set_got_rex64"): Support Intel asm syntax.
("set_rip_rex64"): Likewise.
("set_got_offset_rex64"): Likewise.
("*sibcall_1_rex64_v"): Print register prefix only with AT&T asm
syntax.
("*tls_global_dynamic_64"): Likewise.
("*tls_local_dynamic_base_64"): Likewise.
("*load_tp_si")("*load_tp_di"): Likewise.
("*add_tp_si")("*add_tp_di"): Likewise.
("*tls_dynamic_lea_64"): Likewise.
("*sibcall_value_1_rex64_v"): Likewise.
("stack_tls_protect_set_si"): Likewise.
("stack_tls_protect_set_di"): Likewise.
("stack_tls_protect_test_si"): Likewise.
("stack_tls_protect_test_di"): Likewise.
* config/i386/mmx.md ("*mov<mode>_internal_rex64"): Fix Intel asm
syntax output.
("*movv2sf_internal_rex64"): Likewise.
* config/i386/cpuid.h (__cpuid): Support Intel asm syntax.
(__get_cpuid_max): Likewise.
From-SVN: r129548
This commit is contained in:
Rask Ingemann Lambertsen
Rask Ingemann Lambertsen
parent
cc6c53a3f7
commit
9ad5e54f95
@ -1,3 +1,40 @@
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2007-10-22 Rask Ingemann Lambertsen <rask@sygehus.dk>
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PR target/29473
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PR target/29493
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* config/i386/i386.c (output_pic_addr_const): Support Intel asm syntax.
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(print_reg): Print register prefix only with AT&T asm syntax.
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Support pc_rtx for RIP register.
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(print_operand_address): Use print_reg()'s pc_rtx support for RIP
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relative addressing. Always print segment register prefix with AT&T
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asm syntax and never with Intel asm syntax.
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(print_operand): Suppress 'XXX PTR' prefix for BLKmode operands.
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Fix prefix for 16-byte XFmode operands.
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(output_addr_const_extra): Support Intel asm syntax.
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(x86_file_start): Don't use register prefix with Intel asm syntax.
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* config/i386/i386.md ("*zero_extendqihi2_movzbl"): Fix typo.
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("return_internal_long"): Fix Intel asm syntax output.
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("set_got_rex64"): Support Intel asm syntax.
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("set_rip_rex64"): Likewise.
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("set_got_offset_rex64"): Likewise.
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("*sibcall_1_rex64_v"): Print register prefix only with AT&T asm
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syntax.
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("*tls_global_dynamic_64"): Likewise.
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("*tls_local_dynamic_base_64"): Likewise.
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("*load_tp_si")("*load_tp_di"): Likewise.
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("*add_tp_si")("*add_tp_di"): Likewise.
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("*tls_dynamic_lea_64"): Likewise.
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("*sibcall_value_1_rex64_v"): Likewise.
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("stack_tls_protect_set_si"): Likewise.
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("stack_tls_protect_set_di"): Likewise.
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("stack_tls_protect_test_si"): Likewise.
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("stack_tls_protect_test_di"): Likewise.
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* config/i386/mmx.md ("*mov<mode>_internal_rex64"): Fix Intel asm
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syntax output.
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("*movv2sf_internal_rex64"): Likewise.
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* config/i386/cpuid.h (__cpuid): Support Intel asm syntax.
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(__get_cpuid_max): Likewise.
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2007-10-21 Richard Sandiford <rsandifo@nildram.co.uk>
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* config/mips/mips-protos.h (mips_regno_mode_ok_for_base_p): Give
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@ -62,9 +62,9 @@
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#if defined(__i386__) && defined(__PIC__)
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/* %ebx may be the PIC register. */
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#define __cpuid(level, a, b, c, d) \
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__asm__ ("xchgl\t%%ebx, %1\n\t" \
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__asm__ ("xchg{l}\t{%%}ebx, %1\n\t" \
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"cpuid\n\t" \
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"xchgl\t%%ebx, %1\n\t" \
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"xchg{l}\t{%%}ebx, %1\n\t" \
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: "=a" (a), "=r" (b), "=c" (c), "=d" (d) \
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: "0" (level))
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#else
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@ -88,16 +88,16 @@ __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
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#ifndef __x86_64__
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/* See if we can use cpuid. On AMD64 we always can. */
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__asm__ ("pushfl\n\t"
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"pushfl\n\t"
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"popl\t%0\n\t"
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"movl\t%0, %1\n\t"
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"xorl\t%2, %0\n\t"
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"pushl\t%0\n\t"
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"popfl\n\t"
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"pushfl\n\t"
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"popl\t%0\n\t"
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"popfl\n\t"
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__asm__ ("pushf{l|d}\n\t"
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"pushf{l|d}\n\t"
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"pop{l}\t%0\n\t"
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"mov{l}\t{%0, %1|%1, %0}\n\t"
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"xor{l}\t{%2, %0|%0, %2}\n\t"
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"push{l}\t%0\n\t"
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"popf{l|d}\n\t"
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"pushf{l|d}\n\t"
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"pop{l}\t%0\n\t"
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"popf{l|d}\n\t"
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: "=&r" (__eax), "=&r" (__ebx)
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: "i" (0x00200000));
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@ -8185,7 +8185,8 @@ output_pic_addr_const (FILE *file, rtx x, int code)
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fputs ("@PLTOFF", file);
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break;
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case UNSPEC_GOTPCREL:
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fputs ("@GOTPCREL(%rip)", file);
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fputs (ASSEMBLER_DIALECT == ASM_ATT ?
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"@GOTPCREL(%rip)" : "@GOTPCREL[rip]", file);
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break;
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case UNSPEC_GOTTPOFF:
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/* FIXME: This might be @TPOFF in Sun ld too. */
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@ -8205,7 +8206,8 @@ output_pic_addr_const (FILE *file, rtx x, int code)
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break;
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case UNSPEC_GOTNTPOFF:
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if (TARGET_64BIT)
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fputs ("@GOTTPOFF(%rip)", file);
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fputs (ASSEMBLER_DIALECT == ASM_ATT ?
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"@GOTTPOFF(%rip)": "@GOTTPOFF[rip]", file);
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else
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fputs ("@GOTNTPOFF", file);
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break;
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@ -8531,15 +8533,23 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse,
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void
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print_reg (rtx x, int code, FILE *file)
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{
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gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
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gcc_assert (x == pc_rtx
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|| (REGNO (x) != ARG_POINTER_REGNUM
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&& REGNO (x) != FRAME_POINTER_REGNUM
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&& REGNO (x) != FLAGS_REG
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&& REGNO (x) != FPSR_REG
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&& REGNO (x) != FPCR_REG);
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&& REGNO (x) != FPCR_REG));
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if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('%', file);
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if (x == pc_rtx)
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{
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gcc_assert (TARGET_64BIT);
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fputs ("rip", file);
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return;
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}
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if (code == 'w' || MMX_REG_P (x))
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code = 2;
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else if (code == 'b')
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@ -9036,8 +9046,9 @@ print_operand (FILE *file, rtx x, int code)
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else if (MEM_P (x))
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{
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/* No `byte ptr' prefix for call instructions. */
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if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P')
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/* No `byte ptr' prefix for call instructions or BLKmode operands. */
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if (ASSEMBLER_DIALECT == ASM_INTEL && code != 'X' && code != 'P'
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&& GET_MODE (x) != BLKmode)
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{
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const char * size;
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switch (GET_MODE_SIZE (GET_MODE (x)))
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@ -9047,7 +9058,12 @@ print_operand (FILE *file, rtx x, int code)
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case 4: size = "DWORD"; break;
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case 8: size = "QWORD"; break;
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case 12: size = "XWORD"; break;
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case 16: size = "XMMWORD"; break;
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case 16:
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if (GET_MODE (x) == XFmode)
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size = "XWORD";
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else
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size = "XMMWORD";
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break;
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default:
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gcc_unreachable ();
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}
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@ -9165,7 +9181,7 @@ print_operand_address (FILE *file, rtx addr)
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break;
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case SEG_FS:
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case SEG_GS:
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if (USER_LABEL_PREFIX[0] == 0)
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('%', file);
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fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file);
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break;
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@ -9173,6 +9189,21 @@ print_operand_address (FILE *file, rtx addr)
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gcc_unreachable ();
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}
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/* Use one byte shorter RIP relative addressing for 64bit mode. */
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if (TARGET_64BIT && !base && !index)
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{
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rtx symbol = disp;
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if (GET_CODE (disp) == CONST
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&& GET_CODE (XEXP (disp, 0)) == PLUS
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&& CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
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symbol = XEXP (XEXP (disp, 0), 0);
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if (GET_CODE (symbol) == LABEL_REF
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|| (GET_CODE (symbol) == SYMBOL_REF
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&& SYMBOL_REF_TLS_MODEL (symbol) == 0))
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base = pc_rtx;
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}
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if (!base && !index)
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{
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/* Displacement only requires special attention. */
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@ -9180,30 +9211,13 @@ print_operand_address (FILE *file, rtx addr)
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if (CONST_INT_P (disp))
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{
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if (ASSEMBLER_DIALECT == ASM_INTEL && parts.seg == SEG_DEFAULT)
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{
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if (USER_LABEL_PREFIX[0] == 0)
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putc ('%', file);
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fputs ("ds:", file);
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}
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fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (disp));
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}
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else if (flag_pic)
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output_pic_addr_const (file, disp, 0);
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else
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output_addr_const (file, disp);
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/* Use one byte shorter RIP relative addressing for 64bit mode. */
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if (TARGET_64BIT)
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{
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if (GET_CODE (disp) == CONST
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&& GET_CODE (XEXP (disp, 0)) == PLUS
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&& CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
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disp = XEXP (XEXP (disp, 0), 0);
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if (GET_CODE (disp) == LABEL_REF
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|| (GET_CODE (disp) == SYMBOL_REF
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&& SYMBOL_REF_TLS_MODEL (disp) == 0))
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fputs ("(%rip)", file);
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}
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}
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else
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{
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@ -9319,7 +9333,8 @@ output_addr_const_extra (FILE *file, rtx x)
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case UNSPEC_GOTNTPOFF:
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output_addr_const (file, op);
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if (TARGET_64BIT)
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fputs ("@GOTTPOFF(%rip)", file);
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fputs (ASSEMBLER_DIALECT == ASM_ATT ?
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"@GOTTPOFF(%rip)" : "@GOTTPOFF[rip]", file);
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else
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fputs ("@GOTNTPOFF", file);
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break;
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@ -22736,7 +22751,7 @@ x86_file_start (void)
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if (X86_FILE_START_FLTUSED)
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fputs ("\t.global\t__fltused\n", asm_out_file);
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if (ix86_asm_dialect == ASM_INTEL)
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fputs ("\t.intel_syntax\n", asm_out_file);
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fputs ("\t.intel_syntax noprefix\n", asm_out_file);
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}
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int
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@ -3439,7 +3439,7 @@
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[(set (match_operand:HI 0 "register_operand" "=r")
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(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
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"(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
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"movz{bl|x}\t{%1, %k0|%k0, %k1}"
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"movz{bl|x}\t{%1, %k0|%k0, %1}"
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[(set_attr "type" "imovx")
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(set_attr "mode" "SI")])
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@ -14907,7 +14907,7 @@
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[(call (mem:QI (reg:DI R11_REG))
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(match_operand 0 "" ""))]
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"SIBLING_CALL_P (insn) && TARGET_64BIT"
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"jmp\t*%%r11"
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"jmp\t{*%%}r11"
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[(set_attr "type" "call")])
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@ -15037,7 +15037,7 @@
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[(return)
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(unspec [(const_int 0)] UNSPEC_REP)]
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"reload_completed"
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"rep{\;| }ret"
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"rep\;ret"
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[(set_attr "length" "1")
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(set_attr "length_immediate" "0")
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(set_attr "prefix_rep" "1")
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@ -15116,7 +15116,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_SET_GOT))]
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"TARGET_64BIT"
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"lea{q}\t_GLOBAL_OFFSET_TABLE_(%%rip), %0"
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"lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
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[(set_attr "type" "lea")
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(set_attr "length" "6")])
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@ -15124,7 +15124,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_RIP))]
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"TARGET_64BIT"
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"lea{q}\t%l1(%%rip), %0"
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"lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
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[(set_attr "type" "lea")
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(set_attr "length" "6")])
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@ -15132,7 +15132,7 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(match_operand:DI 1 "" "")] UNSPEC_SET_GOT_OFFSET))]
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"TARGET_64BIT"
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"movabs{q}\t$_GLOBAL_OFFSET_TABLE_-%l1, %0"
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"movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
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[(set_attr "type" "imov")
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(set_attr "length" "11")])
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@ -15753,7 +15753,7 @@
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(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
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UNSPEC_TLS_GD)]
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"TARGET_64BIT"
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".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|%%rdi, %a1@TLSGD[%%rip]}\;.word\t0x6666\;rex64\;call\t%P2"
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".byte\t0x66\;lea{q}\t{%a1@TLSGD(%%rip), %%rdi|rdi, %a1@TLSGD[rip]}\;.word\t0x6666\;rex64\;call\t%P2"
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[(set_attr "type" "multi")
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(set_attr "length" "16")])
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@ -15831,7 +15831,7 @@
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(match_operand:DI 2 "" "")))
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(unspec:DI [(const_int 0)] UNSPEC_TLS_LD_BASE)]
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"TARGET_64BIT"
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"lea{q}\t{%&@TLSLD(%%rip), %%rdi|%%rdi, %&@TLSLD[%%rip]}\;call\t%P1"
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"lea{q}\t{%&@TLSLD(%%rip), %%rdi|rdi, %&@TLSLD[rip]}\;call\t%P1"
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[(set_attr "type" "multi")
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(set_attr "length" "12")])
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@ -15881,7 +15881,7 @@
|
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const_int 0)] UNSPEC_TP))]
|
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"!TARGET_64BIT"
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"mov{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
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"mov{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
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@ -15894,7 +15894,7 @@
|
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(match_operand:SI 1 "register_operand" "0")))
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(clobber (reg:CC FLAGS_REG))]
|
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"!TARGET_64BIT"
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"add{l}\t{%%gs:0, %0|%0, DWORD PTR %%gs:0}"
|
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"add{l}\t{%%gs:0, %0|%0, DWORD PTR gs:0}"
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[(set_attr "type" "alu")
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(set_attr "modrm" "0")
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(set_attr "length" "7")
|
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@ -15905,7 +15905,7 @@
|
||||
[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec:DI [(const_int 0)] UNSPEC_TP))]
|
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"TARGET_64BIT"
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"mov{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
|
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"mov{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
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[(set_attr "type" "imov")
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(set_attr "modrm" "0")
|
||||
(set_attr "length" "7")
|
||||
@ -15918,7 +15918,7 @@
|
||||
(match_operand:DI 1 "register_operand" "0")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_64BIT"
|
||||
"add{q}\t{%%fs:0, %0|%0, QWORD PTR %%fs:0}"
|
||||
"add{q}\t{%%fs:0, %0|%0, QWORD PTR fs:0}"
|
||||
[(set_attr "type" "alu")
|
||||
(set_attr "modrm" "0")
|
||||
(set_attr "length" "7")
|
||||
@ -16014,7 +16014,7 @@
|
||||
(unspec:DI [(match_operand:DI 1 "tls_symbolic_operand" "")]
|
||||
UNSPEC_TLSDESC))]
|
||||
"TARGET_64BIT && TARGET_GNU2_TLS"
|
||||
"lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[%%rip]}"
|
||||
"lea{q}\t{%a1@TLSDESC(%%rip), %0|%0, %a1@TLSDESC[rip]}"
|
||||
[(set_attr "type" "lea")
|
||||
(set_attr "mode" "DI")
|
||||
(set_attr "length" "7")
|
||||
@ -21262,7 +21262,7 @@
|
||||
(call (mem:QI (reg:DI R11_REG))
|
||||
(match_operand:DI 1 "" "")))]
|
||||
"SIBLING_CALL_P (insn) && TARGET_64BIT"
|
||||
"jmp\t*%%r11"
|
||||
"jmp\t{*%%}r11"
|
||||
[(set_attr "type" "callv")])
|
||||
|
||||
;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
|
||||
@ -21470,7 +21470,7 @@
|
||||
(set (match_scratch:SI 2 "=&r") (const_int 0))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
""
|
||||
"mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR %%gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
|
||||
"mov{l}\t{%%gs:%P1, %2|%2, DWORD PTR gs:%P1}\;mov{l}\t{%2, %0|%0, %2}\;xor{l}\t%2, %2"
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
(define_insn "stack_tls_protect_set_di"
|
||||
@ -21484,9 +21484,9 @@
|
||||
system call would not have to trash the userspace segment register,
|
||||
which would be expensive */
|
||||
if (ix86_cmodel != CM_KERNEL)
|
||||
return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR %%fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
|
||||
return "mov{q}\t{%%fs:%P1, %2|%2, QWORD PTR fs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
|
||||
else
|
||||
return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR %%gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
|
||||
return "mov{q}\t{%%gs:%P1, %2|%2, QWORD PTR gs:%P1}\;mov{q}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2";
|
||||
}
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
@ -21545,7 +21545,7 @@
|
||||
UNSPEC_SP_TLS_TEST))
|
||||
(clobber (match_scratch:SI 3 "=r"))]
|
||||
""
|
||||
"mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR %%gs:%P2}"
|
||||
"mov{l}\t{%1, %3|%3, %1}\;xor{l}\t{%%gs:%P2, %3|%3, DWORD PTR gs:%P2}"
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
(define_insn "stack_tls_protect_test_di"
|
||||
@ -21560,9 +21560,9 @@
|
||||
system call would not have to trash the userspace segment register,
|
||||
which would be expensive */
|
||||
if (ix86_cmodel != CM_KERNEL)
|
||||
return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR %%fs:%P2}";
|
||||
return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%fs:%P2, %3|%3, QWORD PTR fs:%P2}";
|
||||
else
|
||||
return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR %%gs:%P2}";
|
||||
return "mov{q}\t{%1, %3|%3, %1}\;xor{q}\t{%%gs:%P2, %3|%3, QWORD PTR gs:%P2}";
|
||||
}
|
||||
[(set_attr "type" "multi")])
|
||||
|
||||
|
||||
@ -69,8 +69,8 @@
|
||||
"TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
movq\t{%1, %0|%0, %1}
|
||||
movq\t{%1, %0|%0, %1}
|
||||
mov{q}\t{%1, %0|%0, %1}
|
||||
mov{q}\t{%1, %0|%0, %1}
|
||||
pxor\t%0, %0
|
||||
movq\t{%1, %0|%0, %1}
|
||||
movq\t{%1, %0|%0, %1}
|
||||
@ -128,8 +128,8 @@
|
||||
"TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
movq\t{%1, %0|%0, %1}
|
||||
movq\t{%1, %0|%0, %1}
|
||||
mov{q}\t{%1, %0|%0, %1}
|
||||
mov{q}\t{%1, %0|%0, %1}
|
||||
pxor\t%0, %0
|
||||
movq\t{%1, %0|%0, %1}
|
||||
movq\t{%1, %0|%0, %1}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user