amdgcn: Support XNACK mode
The XNACK feature allows memory load instructions to restart safely following a page-miss interrupt. This is useful for shared-memory devices, like APUs, and to implement OpenMP Unified Shared Memory. To support the feature we must be able to set the appropriate meta-data and set the load instructions to early-clobber. When the port supports scheduling of s_waitcnt instructions there will be further requirements. gcc/ChangeLog: * config/gcn/gcn-hsa.h (XNACKOPT): New macro. (ASM_SPEC): Use XNACKOPT. * config/gcn/gcn-opts.h (enum sram_ecc_type): Rename to ... (enum hsaco_attr_type): ... this, and generalize the names. (TARGET_XNACK): New macro. * config/gcn/gcn-valu.md (gather<mode>_insn_1offset<exec>): Add xnack compatible alternatives. (gather<mode>_insn_2offsets<exec>): Likewise. * config/gcn/gcn.c (gcn_option_override): Permit -mxnack for devices other than Fiji. (gcn_expand_epilogue): Remove early-clobber problems. (output_file_start): Emit xnack attributes. (gcn_hsa_declare_function_name): Obey -mxnack setting. * config/gcn/gcn.md (xnack): New attribute. (enabled): Rework to include "xnack" attribute. (*movbi): Add xnack compatible alternatives. (*mov<mode>_insn): Likewise. (*mov<mode>_insn): Likewise. (*mov<mode>_insn): Likewise. (*movti_insn): Likewise. * config/gcn/gcn.opt (-mxnack): Add the "on/off/any" syntax. (sram_ecc_type): Rename to ... (hsaco_attr_type: ... this.) * config/gcn/mkoffload.c (SET_XNACK_ANY): New macro. (TEST_XNACK): Delete. (TEST_XNACK_ANY): New macro. (TEST_XNACK_ON): New macro. (main): Support the new -mxnack=on/off/any syntax.
This commit is contained in:
Andrew Stubbs
parent
88c73dbc2d
commit
9aefadc9e6
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@ -81,12 +81,13 @@ extern unsigned int gcn_local_sym_hash (const char *name);
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/* In HSACOv4 no attribute setting means the binary supports "any" hardware
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configuration. The name of the attribute also changed. */
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#define SRAMOPT "msram-ecc=on:-mattr=+sramecc;msram-ecc=off:-mattr=-sramecc"
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#define XNACKOPT "mxnack=on:-mattr=+xnack;mxnack=off:-mattr=-xnack"
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/* Use LLVM assembler and linker options. */
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#define ASM_SPEC "-triple=amdgcn--amdhsa " \
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"%:last_arg(%{march=*:-mcpu=%*}) " \
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"%{!march=*|march=fiji:--amdhsa-code-object-version=3} " \
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"%{" NO_XNACK "mxnack:-mattr=+xnack;:-mattr=-xnack} " \
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"%{" NO_XNACK XNACKOPT "}" \
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"%{" NO_SRAM_ECC SRAMOPT "} " \
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"-filetype=obj"
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#define LINK_SPEC "--pie --export-dynamic"
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@ -48,11 +48,13 @@ extern enum gcn_isa {
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#define TARGET_M0_LDS_LIMIT (TARGET_GCN3)
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#define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS)
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enum sram_ecc_type
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#define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF)
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enum hsaco_attr_type
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{
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SRAM_ECC_OFF,
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SRAM_ECC_ON,
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SRAM_ECC_ANY
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HSACO_ATTR_OFF,
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HSACO_ATTR_ON,
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HSACO_ATTR_ANY
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};
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#endif
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@ -741,13 +741,13 @@
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{})
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(define_insn "gather<mode>_insn_1offset<exec>"
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[(set (match_operand:V_ALL 0 "register_operand" "=v")
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[(set (match_operand:V_ALL 0 "register_operand" "=v,&v")
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(unspec:V_ALL
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[(plus:<VnDI> (match_operand:<VnDI> 1 "register_operand" " v")
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[(plus:<VnDI> (match_operand:<VnDI> 1 "register_operand" " v, v")
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(vec_duplicate:<VnDI>
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(match_operand 2 "immediate_operand" " n")))
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(match_operand 3 "immediate_operand" " n")
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(match_operand 4 "immediate_operand" " n")
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(match_operand 2 "immediate_operand" " n, n")))
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(match_operand 3 "immediate_operand" " n, n")
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(match_operand 4 "immediate_operand" " n, n")
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(mem:BLK (scratch))]
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UNSPEC_GATHER))]
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"(AS_FLAT_P (INTVAL (operands[3]))
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@ -777,7 +777,8 @@
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return buf;
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}
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[(set_attr "type" "flat")
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(set_attr "length" "12")])
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(set_attr "length" "12")
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(set_attr "xnack" "off,on")])
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(define_insn "gather<mode>_insn_1offset_ds<exec>"
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[(set (match_operand:V_ALL 0 "register_operand" "=v")
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@ -802,17 +803,18 @@
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(set_attr "length" "12")])
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(define_insn "gather<mode>_insn_2offsets<exec>"
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[(set (match_operand:V_ALL 0 "register_operand" "=v")
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[(set (match_operand:V_ALL 0 "register_operand" "=v,&v")
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(unspec:V_ALL
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[(plus:<VnDI>
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(plus:<VnDI>
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(vec_duplicate:<VnDI>
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(match_operand:DI 1 "register_operand" "Sv"))
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(match_operand:DI 1 "register_operand" "Sv,Sv"))
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(sign_extend:<VnDI>
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(match_operand:<VnSI> 2 "register_operand" " v")))
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(vec_duplicate:<VnDI> (match_operand 3 "immediate_operand" " n")))
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(match_operand 4 "immediate_operand" " n")
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(match_operand 5 "immediate_operand" " n")
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(match_operand:<VnSI> 2 "register_operand" " v, v")))
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(vec_duplicate:<VnDI> (match_operand 3 "immediate_operand"
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" n, n")))
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(match_operand 4 "immediate_operand" " n, n")
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(match_operand 5 "immediate_operand" " n, n")
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(mem:BLK (scratch))]
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UNSPEC_GATHER))]
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"(AS_GLOBAL_P (INTVAL (operands[4]))
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@ -831,7 +833,8 @@
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return buf;
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}
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[(set_attr "type" "flat")
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(set_attr "length" "12")])
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(set_attr "length" "12")
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(set_attr "xnack" "off,on")])
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(define_expand "scatter_store<mode><vnsi>"
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[(match_operand:DI 0 "register_operand")
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@ -170,9 +170,14 @@ gcn_option_override (void)
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acc_lds_size = 32768;
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}
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/* The xnack option is a placeholder, for now. */
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if (flag_xnack)
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sorry ("XNACK support");
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/* gfx908 "Fiji" does not support XNACK. */
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if (gcn_arch == PROCESSOR_FIJI)
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{
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if (flag_xnack == HSACO_ATTR_ON)
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error ("-mxnack=on is incompatible with -march=fiji");
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/* Allow HSACO_ATTR_ANY silently because that's the default. */
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flag_xnack = HSACO_ATTR_OFF;
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}
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}
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/* }}} */
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@ -3187,17 +3192,19 @@ gcn_expand_epilogue (void)
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/* Assume that an exit value compatible with gcn-run is expected.
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That is, the third input parameter is an int*.
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We can't allocate any new registers, but the kernarg_reg is
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dead after this, so we'll use that. */
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We can't allocate any new registers, but the dispatch_ptr and
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kernarg_reg are dead after this, so we'll use those. */
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rtx dispatch_ptr_reg = gen_rtx_REG (DImode, cfun->machine->args.reg
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[DISPATCH_PTR_ARG]);
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rtx kernarg_reg = gen_rtx_REG (DImode, cfun->machine->args.reg
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[KERNARG_SEGMENT_PTR_ARG]);
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rtx retptr_mem = gen_rtx_MEM (DImode,
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gen_rtx_PLUS (DImode, kernarg_reg,
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GEN_INT (16)));
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set_mem_addr_space (retptr_mem, ADDR_SPACE_SCALAR_FLAT);
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emit_move_insn (kernarg_reg, retptr_mem);
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emit_move_insn (dispatch_ptr_reg, retptr_mem);
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rtx retval_mem = gen_rtx_MEM (SImode, kernarg_reg);
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rtx retval_mem = gen_rtx_MEM (SImode, dispatch_ptr_reg);
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set_mem_addr_space (retval_mem, ADDR_SPACE_SCALAR_FLAT);
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emit_move_insn (retval_mem,
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gen_rtx_REG (SImode, SGPR_REGNO (RETURN_VALUE_REG)));
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@ -5222,11 +5229,12 @@ static void
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output_file_start (void)
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{
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/* In HSACOv4 no attribute setting means the binary supports "any" hardware
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configuration. In GCC binaries, this is true for SRAM ECC, but not
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XNACK. */
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const char *xnack = (flag_xnack ? ":xnack+" : ":xnack-");
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const char *sram_ecc = (flag_sram_ecc == SRAM_ECC_ON ? ":sramecc+"
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: flag_sram_ecc == SRAM_ECC_OFF ? ":sramecc-"
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configuration. */
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const char *xnack = (flag_xnack == HSACO_ATTR_ON ? ":xnack+"
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: flag_xnack == HSACO_ATTR_OFF ? ":xnack-"
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: "");
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const char *sram_ecc = (flag_sram_ecc == HSACO_ATTR_ON ? ":sramecc+"
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: flag_sram_ecc == HSACO_ATTR_OFF ? ":sramecc-"
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: "");
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const char *cpu;
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@ -5270,7 +5278,7 @@ void
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gcn_hsa_declare_function_name (FILE *file, const char *name, tree)
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{
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int sgpr, vgpr;
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bool xnack_enabled = false;
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bool xnack_enabled = TARGET_XNACK;
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fputs ("\n\n", file);
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@ -276,12 +276,19 @@
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(define_attr "gcn_version" "gcn3,gcn5" (const_string "gcn3"))
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(define_attr "xnack" "na,off,on" (const_string "na"))
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(define_attr "enabled" ""
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(cond [(eq_attr "gcn_version" "gcn3") (const_int 1)
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(and (eq_attr "gcn_version" "gcn5")
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(ne (symbol_ref "TARGET_GCN5_PLUS") (const_int 0)))
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(const_int 1)]
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(const_int 0)))
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(cond [(and (eq_attr "gcn_version" "gcn5")
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(eq (symbol_ref "TARGET_GCN5_PLUS") (const_int 0)))
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(const_int 0)
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(and (eq_attr "xnack" "off")
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(ne (symbol_ref "TARGET_XNACK") (const_int 0)))
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(const_int 0)
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(and (eq_attr "xnack" "on")
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(eq (symbol_ref "TARGET_XNACK") (const_int 0)))
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(const_int 0)]
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(const_int 1)))
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; We need to be able to identify v_readlane and v_writelane with
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; SGPR lane selection in order to handle "Manually Inserted Wait States".
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@ -470,9 +477,9 @@
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(define_insn "*movbi"
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[(set (match_operand:BI 0 "nonimmediate_operand"
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"=Sg, v,Sg,cs,cV,cV,Sm,RS, v,RF, v,RM")
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"=Sg, v,Sg,cs,cV,cV,Sm,&Sm,RS, v,&v,RF, v,&v,RM")
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(match_operand:BI 1 "gcn_load_operand"
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"SSA,vSvA, v,SS, v,SS,RS,Sm,RF, v,RM, v"))]
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"SSA,vSvA, v,SS, v,SS,RS, RS,Sm,RF,RF, v,RM,RM, v"))]
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""
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{
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/* SCC as an operand is currently not accepted by the LLVM assembler, so
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@ -514,66 +521,77 @@
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return "s_mov_b32\tvcc_lo, %1\;"
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"s_mov_b32\tvcc_hi, 0";
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case 6:
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return "s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)";
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case 7:
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return "s_store_dword\t%1, %A0";
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return "s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)";
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case 8:
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return "flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0";
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return "s_store_dword\t%1, %A0";
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case 9:
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return "flat_store_dword\t%A0, %1%O0%g0";
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case 10:
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return "global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)";
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return "flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0";
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case 11:
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return "flat_store_dword\t%A0, %1%O0%g0";
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case 12:
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case 13:
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return "global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)";
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case 14:
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return "global_store_dword\t%A0, %1%O0%g0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "sop1,vop1,vop3a,sopk,vopc,mult,smem,smem,flat,flat,
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flat,flat")
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(set_attr "exec" "*,*,none,*,*,*,*,*,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,8,12,12,12,12,12,12")])
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[(set_attr "type" "sop1,vop1,vop3a,sopk,vopc,mult,smem,smem,smem,flat,flat,
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flat,flat,flat,flat")
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(set_attr "exec" "*,*,none,*,*,*,*,*,*,*,*,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,8,12,12,12,12,12,12,12,12,12")
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(set_attr "xnack" "*,*,*,*,*,*,off,on,*,off,on,*,off,on,*")])
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; 32bit move pattern
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(define_insn "*mov<mode>_insn"
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[(set (match_operand:SISF 0 "nonimmediate_operand"
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"=SD,SD,SD,SD,RB,Sm,RS,v,Sg, v, v,RF,v,RLRG, v,SD, v,RM")
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"=SD,SD,SD,SD,&SD,RB,Sm,&Sm,RS,v,Sg, v, v,&v,RF,v,RLRG, v,SD, v,&v,RM")
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(match_operand:SISF 1 "gcn_load_operand"
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"SSA, J, B,RB,Sm,RS,Sm,v, v,Sv,RF, v,B, v,RLRG, Y,RM, v"))]
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"SSA, J, B,RB, RB,Sm,RS, RS,Sm,v, v,Sv,RF,RF, v,B, v,RLRG, Y,RM,RM, v"))]
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""
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"@
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s_mov_b32\t%0, %1
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s_movk_i32\t%0, %1
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s_mov_b32\t%0, %1
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s_buffer_load%s0\t%0, s[0:3], %1\;s_waitcnt\tlgkmcnt(0)
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s_buffer_load%s0\t%0, s[0:3], %1\;s_waitcnt\tlgkmcnt(0)
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s_buffer_store%s1\t%1, s[0:3], %0
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s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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s_load_dword\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
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s_store_dword\t%1, %A0
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v_mov_b32\t%0, %1
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_load_dword\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store_dword\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
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ds_write_b32\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
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ds_read_b32\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
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s_mov_b32\t%0, %1
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global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_load_dword\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
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global_store_dword\t%A0, %1%O0%g0"
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[(set_attr "type" "sop1,sopk,sop1,smem,smem,smem,smem,vop1,vop3a,vop3a,flat,
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flat,vop1,ds,ds,sop1,flat,flat")
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(set_attr "exec" "*,*,*,*,*,*,*,*,none,none,*,*,*,*,*,*,*,*")
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(set_attr "length" "4,4,8,12,12,12,12,4,8,8,12,12,8,12,12,8,12,12")])
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[(set_attr "type" "sop1,sopk,sop1,smem,smem,smem,smem,smem,smem,vop1,vop3a,
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vop3a,flat,flat,flat,vop1,ds,ds,sop1,flat,flat,flat")
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(set_attr "exec" "*,*,*,*,*,*,*,*,*,*,none,none,*,*,*,*,*,*,*,*,*,*")
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(set_attr "length"
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"4,4,8,12,12,12,12,12,12,4,8,8,12,12,12,8,12,12,8,12,12,12")
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(set_attr "xnack"
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"*,*,*,off,on,*,off,on,*,*,*,*,off,on,*,*,*,*,*,off,on,*")])
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; 8/16bit move pattern
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; TODO: implement combined load and zero_extend, but *only* for -msram-ecc=on
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(define_insn "*mov<mode>_insn"
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[(set (match_operand:QIHI 0 "nonimmediate_operand"
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"=SD,SD,SD,v,Sg, v, v,RF,v,RLRG, v, v,RM")
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"=SD,SD,SD,v,Sg, v, v,&v,RF,v,RLRG, v, v,&v,RM")
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(match_operand:QIHI 1 "gcn_load_operand"
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"SSA, J, B,v, v,Sv,RF, v,B, v,RLRG,RM, v"))]
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"SSA, J, B,v, v,Sv,RF,RF, v,B, v,RLRG,RM,RM, v"))]
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"gcn_valid_move_p (<MODE>mode, operands[0], operands[1])"
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"@
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s_mov_b32\t%0, %1
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@ -583,24 +601,27 @@
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v_readlane_b32\t%0, %1, 0
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v_writelane_b32\t%0, %1, 0
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flat_load%o1\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_load%o1\t%0, %A1%O1%g1\;s_waitcnt\t0
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flat_store%s0\t%A0, %1%O0%g0
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v_mov_b32\t%0, %1
|
||||
ds_write%b0\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
|
||||
ds_read%u1\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
|
||||
global_load%o1\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
global_load%o1\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
global_store%s0\t%A0, %1%O0%g0"
|
||||
[(set_attr "type"
|
||||
"sop1,sopk,sop1,vop1,vop3a,vop3a,flat,flat,vop1,ds,ds,flat,flat")
|
||||
(set_attr "exec" "*,*,*,*,none,none,*,*,*,*,*,*,*")
|
||||
(set_attr "length" "4,4,8,4,4,4,12,12,8,12,12,12,12")])
|
||||
[(set_attr "type" "sop1,sopk,sop1,vop1,vop3a,vop3a,flat,flat,flat,vop1,ds,ds,
|
||||
flat,flat,flat")
|
||||
(set_attr "exec" "*,*,*,*,none,none,*,*,*,*,*,*,*,*,*")
|
||||
(set_attr "length" "4,4,8,4,4,4,12,12,12,8,12,12,12,12,12")
|
||||
(set_attr "xnack" "*,*,*,*,*,*,off,on,*,*,*,*,off,on,*")])
|
||||
|
||||
; 64bit move pattern
|
||||
|
||||
(define_insn_and_split "*mov<mode>_insn"
|
||||
[(set (match_operand:DIDF 0 "nonimmediate_operand"
|
||||
"=SD,SD,SD,RS,Sm,v, v,Sg, v, v,RF,RLRG, v, v,RM")
|
||||
"=SD,SD,SD,RS,Sm,&Sm,v, v,Sg, v, v,&v,RF,RLRG, v, v,&v,RM")
|
||||
(match_operand:DIDF 1 "general_operand"
|
||||
"SSA, C,DB,Sm,RS,v,DB, v,Sv,RF, v, v,RLRG,RM, v"))]
|
||||
"SSA, C,DB,Sm,RS, RS,v,DB, v,Sv,RF,RF, v, v,RLRG,RM,RM, v"))]
|
||||
"GET_CODE(operands[1]) != SYMBOL_REF"
|
||||
"@
|
||||
s_mov_b64\t%0, %1
|
||||
|
|
@ -608,15 +629,18 @@
|
|||
#
|
||||
s_store_dwordx2\t%1, %A0
|
||||
s_load_dwordx2\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
|
||||
s_load_dwordx2\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
|
||||
#
|
||||
#
|
||||
#
|
||||
#
|
||||
flat_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\t0
|
||||
flat_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\t0
|
||||
flat_store_dwordx2\t%A0, %1%O0%g0
|
||||
ds_write_b64\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
|
||||
ds_read_b64\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)
|
||||
global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
global_load_dwordx2\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
global_store_dwordx2\t%A0, %1%O0%g0"
|
||||
"reload_completed
|
||||
&& ((!MEM_P (operands[0]) && !MEM_P (operands[1])
|
||||
|
|
@ -647,29 +671,33 @@
|
|||
operands[3] = inhi;
|
||||
}
|
||||
}
|
||||
[(set_attr "type" "sop1,sop1,mult,smem,smem,vmult,vmult,vmult,vmult,flat,
|
||||
flat,ds,ds,flat,flat")
|
||||
(set_attr "length" "4,8,*,12,12,*,*,*,*,12,12,12,12,12,12")])
|
||||
[(set_attr "type" "sop1,sop1,mult,smem,smem,smem,vmult,vmult,vmult,vmult,
|
||||
flat,flat,flat,ds,ds,flat,flat,flat")
|
||||
(set_attr "length" "4,8,*,12,12,12,*,*,*,*,12,12,12,12,12,12,12,12")
|
||||
(set_attr "xnack" "*,*,*,*,off,on,*,*,*,*,off,on,*,*,*,off,on,*")])
|
||||
|
||||
; 128-bit move.
|
||||
|
||||
(define_insn_and_split "*movti_insn"
|
||||
[(set (match_operand:TI 0 "nonimmediate_operand"
|
||||
"=SD,RS,Sm,RF, v,v, v,SD,RM, v,RL, v")
|
||||
(match_operand:TI 1 "general_operand"
|
||||
"SSB,Sm,RS, v,RF,v,Sv, v, v,RM, v,RL"))]
|
||||
"=SD,RS,Sm,&Sm,RF, v,&v,v, v,SD,RM, v,&v,RL, v")
|
||||
(match_operand:TI 1 "general_operand"
|
||||
"SSB,Sm,RS, RS, v,RF,RF,v,Sv, v, v,RM,RM, v,RL"))]
|
||||
""
|
||||
"@
|
||||
#
|
||||
s_store_dwordx4\t%1, %A0
|
||||
s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
|
||||
s_load_dwordx4\t%0, %A1\;s_waitcnt\tlgkmcnt(0)
|
||||
flat_store_dwordx4\t%A0, %1%O0%g0
|
||||
flat_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\t0
|
||||
flat_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\t0
|
||||
#
|
||||
#
|
||||
#
|
||||
global_store_dwordx4\t%A0, %1%O0%g0
|
||||
global_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
global_load_dwordx4\t%0, %A1%O1%g1\;s_waitcnt\tvmcnt(0)
|
||||
ds_write_b128\t%A0, %1%O0\;s_waitcnt\tlgkmcnt(0)
|
||||
ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)"
|
||||
"reload_completed
|
||||
|
|
@ -691,10 +719,11 @@
|
|||
operands[0] = gcn_operand_part (TImode, operands[0], 0);
|
||||
operands[1] = gcn_operand_part (TImode, operands[1], 0);
|
||||
}
|
||||
[(set_attr "type" "mult,smem,smem,flat,flat,vmult,vmult,vmult,flat,flat,\
|
||||
ds,ds")
|
||||
(set_attr "delayeduse" "*,*,yes,*,*,*,*,*,yes,*,*,*")
|
||||
(set_attr "length" "*,12,12,12,12,*,*,*,12,12,12,12")])
|
||||
[(set_attr "type" "mult,smem,smem,smem,flat,flat,flat,vmult,vmult,vmult,flat,
|
||||
flat,flat,ds,ds")
|
||||
(set_attr "delayeduse" "*,*,yes,yes,*,*,*,*,*,*,*,yes,*,*,*")
|
||||
(set_attr "length" "*,12,12,12,12,12,12,*,*,*,12,12,12,12,12")
|
||||
(set_attr "xnack" "*,*,off,on,*,off,on,*,*,*,*,off,on,*,*")])
|
||||
|
||||
;; }}}
|
||||
;; {{{ Prologue/Epilogue
|
||||
|
|
@ -862,6 +891,8 @@
|
|||
(clobber (reg:BI SCC_REG))]
|
||||
"GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == LABEL_REF"
|
||||
{
|
||||
/* This s_load may not be XNACK-safe on devices where the GOT may fault.
|
||||
DGPUs are most likely fine. */
|
||||
if (SYMBOL_REF_P (operands[1])
|
||||
&& SYMBOL_REF_WEAK (operands[1]))
|
||||
return "s_getpc_b64\t%0\;"
|
||||
|
|
@ -886,6 +917,8 @@
|
|||
{
|
||||
/* !!! These sequences clobber CC_SAVE_REG. */
|
||||
|
||||
/* This s_load may not be XNACK-safe on devices where the GOT may fault.
|
||||
DGPUs are most likely fine. */
|
||||
if (SYMBOL_REF_P (operands[1])
|
||||
&& SYMBOL_REF_WEAK (operands[1]))
|
||||
return "; s_mov_b32\ts22, scc is not supported by the assembler.\;"
|
||||
|
|
|
|||
|
|
@ -86,23 +86,23 @@ Wopenacc-dims
|
|||
Target Var(warn_openacc_dims) Warning
|
||||
Warn about invalid OpenACC dimensions.
|
||||
|
||||
mxnack
|
||||
Target Var(flag_xnack) Init(0)
|
||||
Compile for devices requiring XNACK enabled. Default off.
|
||||
|
||||
Enum
|
||||
Name(sram_ecc_type) Type(enum sram_ecc_type)
|
||||
Name(hsaco_attr_type) Type(enum hsaco_attr_type)
|
||||
SRAM-ECC modes:
|
||||
|
||||
EnumValue
|
||||
Enum(sram_ecc_type) String(off) Value(SRAM_ECC_OFF)
|
||||
Enum(hsaco_attr_type) String(off) Value(HSACO_ATTR_OFF)
|
||||
|
||||
EnumValue
|
||||
Enum(sram_ecc_type) String(on) Value(SRAM_ECC_ON)
|
||||
Enum(hsaco_attr_type) String(on) Value(HSACO_ATTR_ON)
|
||||
|
||||
EnumValue
|
||||
Enum(sram_ecc_type) String(any) Value(SRAM_ECC_ANY)
|
||||
Enum(hsaco_attr_type) String(any) Value(HSACO_ATTR_ANY)
|
||||
|
||||
mxnack=
|
||||
Target RejectNegative Joined ToLower Enum(hsaco_attr_type) Var(flag_xnack) Init(HSACO_ATTR_ANY)
|
||||
Compile for devices requiring XNACK enabled. Default off.
|
||||
|
||||
msram-ecc=
|
||||
Target RejectNegative Joined ToLower Enum(sram_ecc_type) Var(flag_sram_ecc) Init(SRAM_ECC_ANY)
|
||||
Target RejectNegative Joined ToLower Enum(hsaco_attr_type) Var(flag_sram_ecc) Init(HSACO_ATTR_ANY)
|
||||
Compile for devices with the SRAM ECC feature enabled, or not. Default \"any\".
|
||||
|
|
|
|||
|
|
@ -72,10 +72,14 @@
|
|||
|
||||
#define SET_XNACK_ON(VAR) VAR = ((VAR & ~EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
| EF_AMDGPU_FEATURE_XNACK_ON_V4)
|
||||
#define SET_XNACK_ANY(VAR) VAR = ((VAR & ~EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
| EF_AMDGPU_FEATURE_XNACK_ANY_V4)
|
||||
#define SET_XNACK_OFF(VAR) VAR = ((VAR & ~EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
| EF_AMDGPU_FEATURE_XNACK_OFF_V4)
|
||||
#define TEST_XNACK(VAR) ((VAR & EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
== EF_AMDGPU_FEATURE_XNACK_ON_V4)
|
||||
#define TEST_XNACK_ANY(VAR) ((VAR & EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
== EF_AMDGPU_FEATURE_XNACK_ANY_V4)
|
||||
#define TEST_XNACK_ON(VAR) ((VAR & EF_AMDGPU_FEATURE_XNACK_V4) \
|
||||
== EF_AMDGPU_FEATURE_XNACK_ON_V4)
|
||||
|
||||
#define SET_SRAM_ECC_ON(VAR) VAR = ((VAR & ~EF_AMDGPU_FEATURE_SRAMECC_V4) \
|
||||
| EF_AMDGPU_FEATURE_SRAMECC_ON_V4)
|
||||
|
|
@ -881,9 +885,11 @@ main (int argc, char **argv)
|
|||
fPIC = true;
|
||||
else if (strcmp (argv[i], "-fpic") == 0)
|
||||
fpic = true;
|
||||
else if (strcmp (argv[i], "-mxnack") == 0)
|
||||
else if (strcmp (argv[i], "-mxnack=on") == 0)
|
||||
SET_XNACK_ON (elf_flags);
|
||||
else if (strcmp (argv[i], "-mno-xnack") == 0)
|
||||
else if (strcmp (argv[i], "-mxnack=any") == 0)
|
||||
SET_XNACK_ANY (elf_flags);
|
||||
else if (strcmp (argv[i], "-mxnack=off") == 0)
|
||||
SET_XNACK_OFF (elf_flags);
|
||||
else if (strcmp (argv[i], "-msram-ecc=on") == 0)
|
||||
SET_SRAM_ECC_ON (elf_flags);
|
||||
|
|
@ -1042,8 +1048,9 @@ main (int argc, char **argv)
|
|||
obstack_ptr_grow (&ld_argv_obstack, gcn_s2_name);
|
||||
obstack_ptr_grow (&ld_argv_obstack, "-lgomp");
|
||||
obstack_ptr_grow (&ld_argv_obstack,
|
||||
(TEST_XNACK (elf_flags)
|
||||
? "-mxnack" : "-mno-xnack"));
|
||||
(TEST_XNACK_ON (elf_flags) ? "-mxnack=on"
|
||||
: TEST_XNACK_ANY (elf_flags) ? "-mxnack=any"
|
||||
: "-mxnack=off"));
|
||||
obstack_ptr_grow (&ld_argv_obstack,
|
||||
(TEST_SRAM_ECC_ON (elf_flags) ? "-msram-ecc=on"
|
||||
: TEST_SRAM_ECC_ANY (elf_flags) ? "-msram-ecc=any"
|
||||
|
|
|
|||
Loading…
Reference in New Issue