frv.h (enum reg_class): Delete EVEN_ACC_REGS, ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS.
* config/frv/frv.h (enum reg_class): Delete EVEN_ACC_REGS, ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS. (REG_CLASS_NAMES): Likewise. (REG_CLASS_CONTENTS): Likewise. (EVEN_ACC_REGS): New macro. Alias for QUAD_ACC_REGS. (ACC_REGS): New macro. Alias for QUAD_ACC_REGS. (FEVEN_REGS): New macro. Alias for QUAD_ACC_REGS. (FPR_REGS): New macro. Alias for QUAD_ACC_REGS. (EVEN_REGS): New macro. Alias for QUAD_REGS. * config/frv/frv.c (frv_secondary_reload_class): Remove use of duplicate register classes. (frv_class_likely_spileld_p): Likewise. (frv_register_move_cost): Likewise. From-SVN: r173016
This commit is contained in:
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e1ea745113
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@ -1,5 +1,19 @@
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2011-04-27 Nick Clifton <nickc@redhat.com>
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* config/frv/frv.h (enum reg_class): Delete EVEN_ACC_REGS,
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ACC_REGS, FEVEN_REGS, FPR_REGS, EVEN_REGS.
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(REG_CLASS_NAMES): Likewise.
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(REG_CLASS_CONTENTS): Likewise.
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(EVEN_ACC_REGS): New macro. Alias for QUAD_ACC_REGS.
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(ACC_REGS): New macro. Alias for QUAD_ACC_REGS.
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(FEVEN_REGS): New macro. Alias for QUAD_ACC_REGS.
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(FPR_REGS): New macro. Alias for QUAD_ACC_REGS.
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(EVEN_REGS): New macro. Alias for QUAD_REGS.
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* config/frv/frv.c (frv_secondary_reload_class): Remove use of
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duplicate register classes.
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(frv_class_likely_spileld_p): Likewise.
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(frv_register_move_cost): Likewise.
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* config/mcore/mcore.h (REGNO_REG_CLASS): Do not index beyond the
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end of the regno_reg_class array.
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@ -6371,7 +6371,6 @@ frv_secondary_reload_class (enum reg_class rclass,
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/* Accumulators/Accumulator guard registers need to go through floating
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point registers. */
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case QUAD_REGS:
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case EVEN_REGS:
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case GPR_REGS:
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ret = NO_REGS;
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if (x && GET_CODE (x) == REG)
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@ -6385,8 +6384,6 @@ frv_secondary_reload_class (enum reg_class rclass,
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/* Nonzero constants should be loaded into an FPR through a GPR. */
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case QUAD_FPR_REGS:
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case FEVEN_REGS:
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case FPR_REGS:
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if (x && CONSTANT_P (x) && !ZERO_P (x))
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ret = GPR_REGS;
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else
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@ -6406,8 +6403,6 @@ frv_secondary_reload_class (enum reg_class rclass,
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break;
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/* The accumulators need fpr registers. */
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case ACC_REGS:
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case EVEN_ACC_REGS:
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case QUAD_ACC_REGS:
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case ACCG_REGS:
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ret = FPR_REGS;
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@ -6481,8 +6476,6 @@ frv_class_likely_spilled_p (reg_class_t rclass)
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case LR_REG:
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case SPR_REGS:
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case QUAD_ACC_REGS:
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case EVEN_ACC_REGS:
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case ACC_REGS:
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case ACCG_REGS:
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return true;
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}
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@ -6842,19 +6835,16 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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break;
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case QUAD_REGS:
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case EVEN_REGS:
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case GPR_REGS:
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switch (to)
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{
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default:
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break;
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case QUAD_REGS:
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case EVEN_REGS:
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case QUAD_REGS:
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case GPR_REGS:
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return LOW_COST;
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case FEVEN_REGS:
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case FPR_REGS:
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return LOW_COST;
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@ -6864,24 +6854,19 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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return LOW_COST;
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}
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case FEVEN_REGS:
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case FPR_REGS:
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case QUAD_FPR_REGS:
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switch (to)
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{
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default:
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break;
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case QUAD_REGS:
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case EVEN_REGS:
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case GPR_REGS:
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case ACC_REGS:
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case EVEN_ACC_REGS:
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case QUAD_ACC_REGS:
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case ACCG_REGS:
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return MEDIUM_COST;
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case FEVEN_REGS:
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case FPR_REGS:
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case QUAD_FPR_REGS:
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return LOW_COST;
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}
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@ -6894,13 +6879,10 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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break;
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case QUAD_REGS:
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case EVEN_REGS:
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case GPR_REGS:
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return MEDIUM_COST;
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}
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case ACC_REGS:
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case EVEN_ACC_REGS:
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case QUAD_ACC_REGS:
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case ACCG_REGS:
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switch (to)
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@ -6908,8 +6890,7 @@ frv_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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default:
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break;
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case FEVEN_REGS:
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case FPR_REGS:
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case QUAD_FPR_REGS:
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return MEDIUM_COST;
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}
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@ -864,14 +864,9 @@ enum reg_class
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FDPIC_CALL_REGS,
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SPR_REGS,
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QUAD_ACC_REGS,
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EVEN_ACC_REGS,
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ACC_REGS,
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ACCG_REGS,
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QUAD_FPR_REGS,
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FEVEN_REGS,
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FPR_REGS,
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QUAD_REGS,
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EVEN_REGS,
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GPR_REGS,
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ALL_REGS,
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LIM_REG_CLASSES
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@ -904,14 +899,9 @@ enum reg_class
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"FDPIC_CALL_REGS", \
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"SPR_REGS", \
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"QUAD_ACC_REGS", \
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"EVEN_ACC_REGS", \
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"ACC_REGS", \
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"ACCG_REGS", \
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"QUAD_FPR_REGS", \
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"FEVEN_REGS", \
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"FPR_REGS", \
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"QUAD_REGS", \
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"EVEN_REGS", \
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"GPR_REGS", \
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"ALL_REGS" \
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}
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@ -945,18 +935,19 @@ enum reg_class
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{ 0x0000c000,0x00000000,0x00000000,0x00000000,0x00000000,0x0}, /* FDPIC_CALL_REGS */\
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{ 0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x1e00}, /* SPR_REGS */\
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{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* QUAD_ACC */\
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{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* EVEN_ACC */\
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{ 0x00000000,0x00000000,0x00000000,0x00000000,0x0fff0000,0x0}, /* ACC_REGS */\
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{ 0x00000000,0x00000000,0x00000000,0x00000000,0xf0000000,0xff}, /* ACCG_REGS*/\
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{ 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* QUAD_FPR */\
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{ 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FEVEN_REG*/\
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{ 0x00000000,0x00000000,0xffffffff,0xffffffff,0x00000000,0x0}, /* FPR_REGS */\
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{ 0x0ffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* QUAD_REGS*/\
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{ 0xfffffffc,0xffffffff,0x00000000,0x00000000,0x00000000,0x0}, /* EVEN_REGS*/\
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{ 0xffffffff,0xffffffff,0x00000000,0x00000000,0x00000000,0x100}, /* GPR_REGS */\
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{ 0xffffffff,0xffffffff,0xffffffff,0xffffffff,0xffffffff,0x1fff}, /* ALL_REGS */\
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}
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#define EVEN_ACC_REGS QUAD_ACC_REGS
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#define ACC_REGS QUAD_ACC_REGS
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#define FEVEN_REGS QUAD_FPR_REGS
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#define FPR_REGS QUAD_FPR_REGS
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#define EVEN_REGS QUAD_REGS
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/* A C expression whose value is a register class containing hard register
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REGNO. In general there is more than one such class; choose a class which
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is "minimal", meaning that no smaller class also contains the register. */
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