Initial revision
From-SVN: r350
This commit is contained in:
Richard Stallman
parent
0aaa6af8c2
commit
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296
gcc/config/vax/vax.c
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296
gcc/config/vax/vax.c
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/* Subroutines for insn-output.c for Vax.
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Copyright (C) 1987 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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/* Return 1 if the operand is a REG, a SUBREG, or a MEM that is does not
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have an index. This is used when we are using an operand in a different
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mode than the hardware expects. See jlbc/jlbs.
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This is nonimmedate_operand with a restriction on the type of MEM. */
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int
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reg_or_nxmem_operand (op, mode)
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rtx op;
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enum machine_mode mode;
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{
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if (! nonimmediate_operand (op, mode))
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return 0;
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if (GET_CODE (op) != MEM)
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return 1;
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GO_IF_NONINDEXED_ADDRESS (XEXP (op, 0), nonidx);
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return 0;
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nonidx:
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return 1;
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}
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void
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split_quadword_operands (operands, low, n)
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rtx *operands, *low;
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int n;
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{
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int i;
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/* Split operands. */
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low[0] = low[1] = low[2] = 0;
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for (i = 0; i < 3; i++)
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{
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if (low[i])
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/* it's already been figured out */;
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else if (GET_CODE (operands[i]) == MEM
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&& (GET_CODE (XEXP (operands[i], 0)) == POST_INC))
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{
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rtx addr = XEXP (operands[i], 0);
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operands[i] = low[i] = gen_rtx (MEM, SImode, addr);
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if (which_alternative == 0 && i == 0)
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{
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addr = XEXP (operands[i], 0);
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operands[i+1] = low[i+1] = gen_rtx (MEM, SImode, addr);
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}
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}
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else
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{
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low[i] = operand_subword (operands[i], 0, 0, DImode);
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operands[i] = operand_subword (operands[i], 1, 0, DImode);
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}
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}
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}
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print_operand_address (file, addr)
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FILE *file;
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register rtx addr;
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{
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register rtx reg1, reg2, breg, ireg;
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rtx offset;
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retry:
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switch (GET_CODE (addr))
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{
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case MEM:
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fprintf (file, "*");
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addr = XEXP (addr, 0);
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goto retry;
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case REG:
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fprintf (file, "(%s)", reg_names[REGNO (addr)]);
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break;
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case PRE_DEC:
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fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]);
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break;
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case POST_INC:
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fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]);
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break;
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case PLUS:
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/* There can be either two or three things added here. One must be a
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REG. One can be either a REG or a MULT of a REG and an appropriate
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constant, and the third can only be a constant or a MEM.
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We get these two or three things and put the constant or MEM in
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OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
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a register and can't tell yet if it is a base or index register,
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put it into REG1. */
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reg1 = 0; ireg = 0; breg = 0; offset = 0;
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if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
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|| GET_CODE (XEXP (addr, 0)) == MEM)
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{
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offset = XEXP (addr, 0);
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addr = XEXP (addr, 1);
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}
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else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
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|| GET_CODE (XEXP (addr, 1)) == MEM)
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{
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offset = XEXP (addr, 1);
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addr = XEXP (addr, 0);
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}
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else if (GET_CODE (XEXP (addr, 1)) == MULT)
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{
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ireg = XEXP (addr, 1);
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addr = XEXP (addr, 0);
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}
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else if (GET_CODE (XEXP (addr, 0)) == MULT)
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{
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ireg = XEXP (addr, 0);
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addr = XEXP (addr, 1);
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}
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else if (GET_CODE (XEXP (addr, 1)) == REG)
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{
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reg1 = XEXP (addr, 1);
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addr = XEXP (addr, 0);
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}
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else
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abort ();
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if (GET_CODE (addr) == REG)
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{
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if (reg1)
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ireg = addr;
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else
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reg1 = addr;
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}
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else if (GET_CODE (addr) == MULT)
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ireg = addr;
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else if (GET_CODE (addr) == PLUS)
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{
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if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
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|| GET_CODE (XEXP (addr, 0)) == MEM)
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{
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if (offset)
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{
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if (GET_CODE (offset) == CONST_INT)
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offset = plus_constant (XEXP (addr, 0), INTVAL (offset));
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else if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
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offset = plus_constant (offset, INTVAL (XEXP (addr, 0)));
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else
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abort ();
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}
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offset = XEXP (addr, 0);
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}
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else if (GET_CODE (XEXP (addr, 0)) == REG)
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{
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if (reg1)
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ireg = reg1, breg = XEXP (addr, 0), reg1 = 0;
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else
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reg1 = XEXP (addr, 0);
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}
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else if (GET_CODE (XEXP (addr, 0)) == MULT)
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{
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if (ireg)
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abort ();
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ireg = XEXP (addr, 0);
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}
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else
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abort ();
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if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
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|| GET_CODE (XEXP (addr, 1)) == MEM)
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{
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if (offset)
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{
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if (GET_CODE (offset) == CONST_INT)
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offset = plus_constant (XEXP (addr, 1), INTVAL (offset));
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else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
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offset = plus_constant (offset, INTVAL (XEXP (addr, 1)));
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else
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abort ();
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}
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offset = XEXP (addr, 1);
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}
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else if (GET_CODE (XEXP (addr, 1)) == REG)
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{
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if (reg1)
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ireg = reg1, breg = XEXP (addr, 1), reg1 = 0;
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else
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reg1 = XEXP (addr, 1);
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}
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else if (GET_CODE (XEXP (addr, 1)) == MULT)
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{
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if (ireg)
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abort ();
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ireg = XEXP (addr, 1);
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}
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else
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abort ();
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}
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else
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abort ();
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/* If REG1 is non-zero, figure out if it is a base or index register. */
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if (reg1)
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{
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if (breg != 0 || (offset && GET_CODE (offset) == MEM))
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{
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if (ireg)
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abort ();
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ireg = reg1;
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}
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else
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breg = reg1;
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}
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if (offset != 0)
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output_address (offset);
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if (breg != 0)
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fprintf (file, "(%s)", reg_names[REGNO (breg)]);
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if (ireg != 0)
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{
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if (GET_CODE (ireg) == MULT)
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ireg = XEXP (ireg, 0);
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if (GET_CODE (ireg) != REG)
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abort ();
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fprintf (file, "[%s]", reg_names[REGNO (ireg)]);
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}
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break;
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default:
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output_addr_const (file, addr);
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}
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}
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char *
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rev_cond_name (op)
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rtx op;
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{
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switch (GET_CODE (op))
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{
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case EQ:
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return "neq";
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case NE:
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return "eql";
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case LT:
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return "geq";
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case LE:
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return "gtr";
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case GT:
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return "leq";
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case GE:
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return "lss";
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case LTU:
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return "gequ";
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case LEU:
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return "gtru";
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case GTU:
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return "lequ";
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case GEU:
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return "lssu";
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default:
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abort ();
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}
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}
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