arm: MVE: Fix v[id]wdup's
This patch fixes v[id]wdup intrinsics. They had two issues: 1) the predicated versions did not link the incoming inactive vector parameter to the output 2) The backend didn't enforce the wrap limit operand be in an odd register. 1) was fixed like we did for all other predicated intrinsics 2) requires a temporary hack where we pass the value in the top end of DImode operand. The proper fix would be to add a register CLASS but this interacted badly with other existing targets codegen. We will look to fix this properly in GCC 11. gcc/ChangeLog: 2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com> * config/arm/arm_mve.h: Fix v[id]wdup intrinsics. * config/arm/mve/md: Fix v[id]wdup patterns.
This commit is contained in:
Andre Simoes Dias Vieira
Andre Vieira
parent
b094133c1c
commit
9ce780efc4
@ -1,3 +1,8 @@
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2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm_mve.h: Fix v[id]wdup intrinsics.
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* config/arm/mve/md: Fix v[id]wdup patterns.
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2020-04-07 Andre Vieira <andre.simoesdiasvieira@arm.com>
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* config/arm/arm.c (output_move_neon): Deal with label + offset cases.
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@ -13585,29 +13585,33 @@ __extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_vdwdupq_m_n_uv4si (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_m_n_uv4si (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13615,8 +13619,9 @@ __extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv4si (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv4si (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13624,8 +13629,9 @@ __extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13633,29 +13639,33 @@ __extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_n_u8 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_vdwdupq_n_uv16qi (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_n_uv16qi (__a, __c, __imm);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_n_u32 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_vdwdupq_n_uv4si (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_n_uv4si (__a, __c, __imm);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_n_u16 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_vdwdupq_n_uv8hi (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_n_uv8hi (__a, __c, __imm);
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_wb_u8 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint8x16_t __res = __builtin_mve_vdwdupq_n_uv16qi (*__a, __b, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv16qi (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint8x16_t __res = __builtin_mve_vdwdupq_n_uv16qi (*__a, __c, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv16qi (*__a, __c, __imm);
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return __res;
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}
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@ -13663,8 +13673,9 @@ __extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_wb_u32 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint32x4_t __res = __builtin_mve_vdwdupq_n_uv4si (*__a, __b, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv4si (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint32x4_t __res = __builtin_mve_vdwdupq_n_uv4si (*__a, __c, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv4si (*__a, __c, __imm);
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return __res;
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}
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@ -13672,8 +13683,9 @@ __extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_wb_u16 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint16x8_t __res = __builtin_mve_vdwdupq_n_uv8hi (*__a, __b, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv8hi (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint16x8_t __res = __builtin_mve_vdwdupq_n_uv8hi (*__a, __c, __imm);
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*__a = __builtin_mve_vdwdupq_wb_uv8hi (*__a, __c, __imm);
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return __res;
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}
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@ -13804,29 +13816,33 @@ __extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_n_u8 (uint8x16_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_viwdupq_m_n_uv16qi (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_m_n_uv16qi (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_n_u32 (uint32x4_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_viwdupq_m_n_uv4si (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_m_n_uv4si (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_n_u16 (uint16x8_t __inactive, uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_viwdupq_m_n_uv8hi (__inactive, __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_m_n_uv8hi (__inactive, __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_wb_u8 (uint8x16_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv16qi (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv16qi (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13834,8 +13850,9 @@ __extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_wb_u32 (uint32x4_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv4si (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv4si (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13843,8 +13860,9 @@ __extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_m_wb_u16 (uint16x8_t __inactive, uint32_t * __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__inactive, *__a, __b, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv8hi (__inactive, *__a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__inactive, *__a, __c, __imm, __p);
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*__a = __builtin_mve_viwdupq_m_wb_uv8hi (__inactive, *__a, __c, __imm, __p);
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return __res;
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}
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@ -13852,29 +13870,33 @@ __extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_n_u8 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_viwdupq_n_uv16qi (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_n_uv16qi (__a, __c, __imm);
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}
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_n_u32 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_viwdupq_n_uv4si (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_n_uv4si (__a, __c, __imm);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_n_u16 (uint32_t __a, uint32_t __b, const int __imm)
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{
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return __builtin_mve_viwdupq_n_uv8hi (__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_viwdupq_n_uv8hi (__a, __c, __imm);
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}
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_wb_u8 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint8x16_t __res = __builtin_mve_viwdupq_n_uv16qi (*__a, __b, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv16qi (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint8x16_t __res = __builtin_mve_viwdupq_n_uv16qi (*__a, __c, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv16qi (*__a, __c, __imm);
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return __res;
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}
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@ -13882,8 +13904,9 @@ __extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_wb_u32 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint32x4_t __res = __builtin_mve_viwdupq_n_uv4si (*__a, __b, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv4si (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint32x4_t __res = __builtin_mve_viwdupq_n_uv4si (*__a, __c, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv4si (*__a, __c, __imm);
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return __res;
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}
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@ -13891,11 +13914,13 @@ __extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_viwdupq_wb_u16 (uint32_t * __a, uint32_t __b, const int __imm)
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{
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uint16x8_t __res = __builtin_mve_viwdupq_n_uv8hi (*__a, __b, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv8hi (*__a, __b, __imm);
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uint64_t __c = ((uint64_t) __b) << 32;
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uint16x8_t __res = __builtin_mve_viwdupq_n_uv8hi (*__a, __c, __imm);
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*__a = __builtin_mve_viwdupq_wb_uv8hi (*__a, __c, __imm);
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return __res;
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}
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__extension__ extern __inline int64x2_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vldrdq_gather_base_wb_s64 (uint64x2_t * __addr, const int __offset)
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@ -14095,30 +14120,34 @@ __extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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__arm_vdwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
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{
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return __builtin_mve_vdwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p);
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uint64_t __c = ((uint64_t) __b) << 32;
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return __builtin_mve_vdwdupq_m_n_uv16qi (__arm_vuninitializedq_u8 (), __a, __c, __imm, __p);
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}
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_vdwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
return __builtin_mve_vdwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
return __builtin_mve_vdwdupq_m_n_uv8hi (__arm_vuninitializedq_u16 (), __a, __c, __imm, __p);
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint32x4_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_vdwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
return __builtin_mve_vdwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
return __builtin_mve_vdwdupq_m_n_uv4si (__arm_vuninitializedq_u32 (), __a, __c, __imm, __p);
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint8x16_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_vdwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint8x16_t __arg1 = vuninitializedq_u8 ();
|
||||
uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint8x16_t __arg1 = __arm_vuninitializedq_u8 ();
|
||||
uint8x16_t __res = __builtin_mve_vdwdupq_m_n_uv16qi (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv16qi (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
@ -14126,9 +14155,10 @@ __extension__ extern __inline uint16x8_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_vdwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint16x8_t __arg1 = vuninitializedq_u16 ();
|
||||
uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint16x8_t __arg1 = __arm_vuninitializedq_u16 ();
|
||||
uint16x8_t __res = __builtin_mve_vdwdupq_m_n_uv8hi (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv8hi (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
@ -14136,9 +14166,10 @@ __extension__ extern __inline uint32x4_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_vdwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint32x4_t __arg1 = vuninitializedq_u32 ();
|
||||
uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint32x4_t __arg1 = __arm_vuninitializedq_u32 ();
|
||||
uint32x4_t __res = __builtin_mve_vdwdupq_m_n_uv4si (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_vdwdupq_m_wb_uv4si (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
@ -14197,30 +14228,34 @@ __extension__ extern __inline uint8x16_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_n_u8 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
return __builtin_mve_viwdupq_m_n_uv16qi (vuninitializedq_u8 (), __a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
return __builtin_mve_viwdupq_m_n_uv16qi (__arm_vuninitializedq_u8 (), __a, __c, __imm, __p);
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint16x8_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_n_u16 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
return __builtin_mve_viwdupq_m_n_uv8hi (vuninitializedq_u16 (), __a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
return __builtin_mve_viwdupq_m_n_uv8hi (__arm_vuninitializedq_u16 (), __a, __c, __imm, __p);
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint32x4_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_n_u32 (uint32_t __a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
return __builtin_mve_viwdupq_m_n_uv4si (vuninitializedq_u32 (), __a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
return __builtin_mve_viwdupq_m_n_uv4si (__arm_vuninitializedq_u32 (), __a, __c, __imm, __p);
|
||||
}
|
||||
|
||||
__extension__ extern __inline uint8x16_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_wb_u8 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint8x16_t __arg1 = vuninitializedq_u8 ();
|
||||
uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv16qi (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint8x16_t __arg1 = __arm_vuninitializedq_u8 ();
|
||||
uint8x16_t __res = __builtin_mve_viwdupq_m_n_uv16qi (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv16qi (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
@ -14228,9 +14263,10 @@ __extension__ extern __inline uint16x8_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_wb_u16 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint16x8_t __arg1 = vuninitializedq_u16 ();
|
||||
uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv8hi (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint16x8_t __arg1 = __arm_vuninitializedq_u16 ();
|
||||
uint16x8_t __res = __builtin_mve_viwdupq_m_n_uv8hi (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv8hi (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
@ -14238,9 +14274,10 @@ __extension__ extern __inline uint32x4_t
|
||||
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
|
||||
__arm_viwdupq_x_wb_u32 (uint32_t *__a, uint32_t __b, const int __imm, mve_pred16_t __p)
|
||||
{
|
||||
uint32x4_t __arg1 = vuninitializedq_u32 ();
|
||||
uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__arg1, *__a, __b, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv4si (__arg1, *__a, __b, __imm, __p);
|
||||
uint64_t __c = ((uint64_t) __b) << 32;
|
||||
uint32x4_t __arg1 = __arm_vuninitializedq_u32 ();
|
||||
uint32x4_t __res = __builtin_mve_viwdupq_m_n_uv4si (__arg1, *__a, __c, __imm, __p);
|
||||
*__a = __builtin_mve_viwdupq_m_wb_uv4si (__arg1, *__a, __c, __imm, __p);
|
||||
return __res;
|
||||
}
|
||||
|
||||
|
||||
@ -9853,7 +9853,7 @@
|
||||
(define_expand "mve_vdwdupq_n_u<mode>"
|
||||
[(match_operand:MVE_2 0 "s_register_operand")
|
||||
(match_operand:SI 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:DI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "mve_imm_selective_upto_8")]
|
||||
"TARGET_HAVE_MVE"
|
||||
{
|
||||
@ -9870,7 +9870,7 @@
|
||||
(define_expand "mve_vdwdupq_wb_u<mode>"
|
||||
[(match_operand:SI 0 "s_register_operand")
|
||||
(match_operand:SI 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:DI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "mve_imm_selective_upto_8")
|
||||
(unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -9888,16 +9888,16 @@
|
||||
(define_insn "mve_vdwdupq_wb_u<mode>_insn"
|
||||
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
|
||||
(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
|
||||
(match_operand:SI 3 "s_register_operand" "r")
|
||||
(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
|
||||
VDWDUPQ))
|
||||
(set (match_operand:SI 1 "s_register_operand" "=e")
|
||||
(unspec:SI [(match_dup 2)
|
||||
(match_dup 3)
|
||||
(subreg:SI (match_dup 3) 4)
|
||||
(match_dup 4)]
|
||||
VDWDUPQ))]
|
||||
"TARGET_HAVE_MVE"
|
||||
"vdwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
|
||||
"vdwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
|
||||
)
|
||||
|
||||
;;
|
||||
@ -9907,7 +9907,7 @@
|
||||
[(match_operand:MVE_2 0 "s_register_operand")
|
||||
(match_operand:MVE_2 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "s_register_operand")
|
||||
(match_operand:DI 3 "s_register_operand")
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8")
|
||||
(match_operand:HI 5 "vpr_register_operand")]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -9927,7 +9927,7 @@
|
||||
[(match_operand:SI 0 "s_register_operand")
|
||||
(match_operand:MVE_2 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "s_register_operand")
|
||||
(match_operand:DI 3 "s_register_operand")
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8")
|
||||
(match_operand:HI 5 "vpr_register_operand")]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -9945,22 +9945,22 @@
|
||||
;;
|
||||
(define_insn "mve_vdwdupq_m_wb_u<mode>_insn"
|
||||
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
|
||||
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
|
||||
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
|
||||
(match_operand:SI 3 "s_register_operand" "1")
|
||||
(match_operand:SI 4 "s_register_operand" "r")
|
||||
(subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
|
||||
(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
|
||||
(match_operand:HI 6 "vpr_register_operand" "Up")]
|
||||
VDWDUPQ_M))
|
||||
(set (match_operand:SI 1 "s_register_operand" "=e")
|
||||
(unspec:SI [(match_dup 2)
|
||||
(match_dup 3)
|
||||
(match_dup 4)
|
||||
(subreg:SI (match_dup 4) 4)
|
||||
(match_dup 5)
|
||||
(match_dup 6)]
|
||||
VDWDUPQ_M))
|
||||
]
|
||||
"TARGET_HAVE_MVE"
|
||||
"vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
|
||||
"vpst\;\tvdwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
|
||||
[(set_attr "type" "mve_move")
|
||||
(set_attr "length""8")])
|
||||
|
||||
@ -9970,7 +9970,7 @@
|
||||
(define_expand "mve_viwdupq_n_u<mode>"
|
||||
[(match_operand:MVE_2 0 "s_register_operand")
|
||||
(match_operand:SI 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:DI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "mve_imm_selective_upto_8")]
|
||||
"TARGET_HAVE_MVE"
|
||||
{
|
||||
@ -9987,7 +9987,7 @@
|
||||
(define_expand "mve_viwdupq_wb_u<mode>"
|
||||
[(match_operand:SI 0 "s_register_operand")
|
||||
(match_operand:SI 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:DI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "mve_imm_selective_upto_8")
|
||||
(unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -10005,16 +10005,16 @@
|
||||
(define_insn "mve_viwdupq_wb_u<mode>_insn"
|
||||
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
|
||||
(unspec:MVE_2 [(match_operand:SI 2 "s_register_operand" "1")
|
||||
(match_operand:SI 3 "s_register_operand" "r")
|
||||
(subreg:SI (match_operand:DI 3 "s_register_operand" "r") 4)
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8" "Rg")]
|
||||
VIWDUPQ))
|
||||
(set (match_operand:SI 1 "s_register_operand" "=e")
|
||||
(unspec:SI [(match_dup 2)
|
||||
(match_dup 3)
|
||||
(subreg:SI (match_dup 3) 4)
|
||||
(match_dup 4)]
|
||||
VIWDUPQ))]
|
||||
"TARGET_HAVE_MVE"
|
||||
"viwdup.u%#<V_sz_elem>\t%q0, %2, %3, %4"
|
||||
"viwdup.u%#<V_sz_elem>\t%q0, %2, %R3, %4"
|
||||
)
|
||||
|
||||
;;
|
||||
@ -10024,7 +10024,7 @@
|
||||
[(match_operand:MVE_2 0 "s_register_operand")
|
||||
(match_operand:MVE_2 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "s_register_operand")
|
||||
(match_operand:DI 3 "s_register_operand")
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8")
|
||||
(match_operand:HI 5 "vpr_register_operand")]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -10044,7 +10044,7 @@
|
||||
[(match_operand:SI 0 "s_register_operand")
|
||||
(match_operand:MVE_2 1 "s_register_operand")
|
||||
(match_operand:SI 2 "s_register_operand")
|
||||
(match_operand:SI 3 "s_register_operand")
|
||||
(match_operand:DI 3 "s_register_operand")
|
||||
(match_operand:SI 4 "mve_imm_selective_upto_8")
|
||||
(match_operand:HI 5 "vpr_register_operand")]
|
||||
"TARGET_HAVE_MVE"
|
||||
@ -10062,24 +10062,25 @@
|
||||
;;
|
||||
(define_insn "mve_viwdupq_m_wb_u<mode>_insn"
|
||||
[(set (match_operand:MVE_2 0 "s_register_operand" "=w")
|
||||
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "w")
|
||||
(unspec:MVE_2 [(match_operand:MVE_2 2 "s_register_operand" "0")
|
||||
(match_operand:SI 3 "s_register_operand" "1")
|
||||
(match_operand:SI 4 "s_register_operand" "r")
|
||||
(subreg:SI (match_operand:DI 4 "s_register_operand" "r") 4)
|
||||
(match_operand:SI 5 "mve_imm_selective_upto_8" "Rg")
|
||||
(match_operand:HI 6 "vpr_register_operand" "Up")]
|
||||
VIWDUPQ_M))
|
||||
(set (match_operand:SI 1 "s_register_operand" "=e")
|
||||
(unspec:SI [(match_dup 2)
|
||||
(match_dup 3)
|
||||
(match_dup 4)
|
||||
(subreg:SI (match_dup 4) 4)
|
||||
(match_dup 5)
|
||||
(match_dup 6)]
|
||||
VIWDUPQ_M))
|
||||
]
|
||||
"TARGET_HAVE_MVE"
|
||||
"vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %4, %5"
|
||||
"vpst\;\tviwdupt.u%#<V_sz_elem>\t%q2, %3, %R4, %5"
|
||||
[(set_attr "type" "mve_move")
|
||||
(set_attr "length""8")])
|
||||
|
||||
(define_expand "mve_vstrwq_scatter_base_wb_<supf>v4si"
|
||||
[(match_operand:V4SI 0 "s_register_operand" "=w")
|
||||
(match_operand:SI 1 "mve_vldrd_immediate" "Ri")
|
||||
|
||||
Loading…
Reference in New Issue
Block a user