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i386.h (TARGET_GENERIC32, [...]): Remove. 

* i386.h (TARGET_GENERIC32, TARGET_GENERIC64): Remove.
	(TARGET_GENERIC): Use PROCESOR_GENERIC
	(enum processor_type): Unify generic32 and 64.
	* i386.md (cpu): Likewise.
	* x86-tune.def (use_leave): Enable for generic32.
	(avoid_vector_decode, slow_imul_imm32_mem, slow_imul_imm8): Likewise.
	* athlon.md: Change generic64 to generic in all occurences.
	* i386-c.c (ix86_target_macros_internal): Unify generic64 and 32.
	(ix86_target_macros_internal): Likewise.
	* driver-i386.c (host_detect_local_cpu): Likewise.
	* i386.c (generic64_memcpy, generic64_memset, generic64_cost): Rename to ..
	(generic_memcpy, generic_memset, generic_cost): This one.
	(generic32_memcpy, generic32_memset, generic32_cost): Remove.
	(m_GENERIC32, m_GENERIC64): Remove.
	(m_GENERIC): Turn into one flag.
	(processor_target): Unify generic tunnings.
	(ix86_option_override_internal): Replace generic32/64 by generic.
	(ix86_issue_rate): Likewise.
	(ix86_adjust_cost): Likewise.

From-SVN: r202741
This commit is contained in:
Jan Hubicka 2013-09-19 14:43:57 +02:00 committed by Jan Hubicka
parent 188c7d00e6
commit 9d5321624b
8 changed files with 147 additions and 240 deletions
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22
gcc/ChangeLog
View File

@ -1,3 +1,25 @@
2013-09-19 Jan Hubicka <jh@suse.cz>
* i386.h (TARGET_GENERIC32, TARGET_GENERIC64): Remove.
(TARGET_GENERIC): Use PROCESOR_GENERIC
(enum processor_type): Unify generic32 and 64.
* i386.md (cpu): Likewise.
* x86-tune.def (use_leave): Enable for generic32.
(avoid_vector_decode, slow_imul_imm32_mem, slow_imul_imm8): Likewise.
* athlon.md: Change generic64 to generic in all occurences.
* i386-c.c (ix86_target_macros_internal): Unify generic64 and 32.
(ix86_target_macros_internal): Likewise.
* driver-i386.c (host_detect_local_cpu): Likewise.
* i386.c (generic64_memcpy, generic64_memset, generic64_cost): Rename to ..
(generic_memcpy, generic_memset, generic_cost): This one.
(generic32_memcpy, generic32_memset, generic32_cost): Remove.
(m_GENERIC32, m_GENERIC64): Remove.
(m_GENERIC): Turn into one flag.
(processor_target): Unify generic tunnings.
(ix86_option_override_internal): Replace generic32/64 by generic.
(ix86_issue_rate): Likewise.
(ix86_adjust_cost): Likewise.
2013-09-19 Jan Hubicka <jh@suse.cz>
* cgraph.c (cgraph_create_edge_1): Avoid uninitialized read

186
gcc/config/i386/athlon.md
View File

@ -151,11 +151,11 @@
;; Jump instructions are executed in the branch unit completely transparent to us
(define_insn_reservation "athlon_branch" 0
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "ibr"))
"athlon-direct,athlon-ieu")
(define_insn_reservation "athlon_call" 0
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "call,callv"))
"athlon-vector,athlon-ieu")
(define_insn_reservation "athlon_call_amdfam10" 0
@ -166,15 +166,15 @@
;; Latency of push operation is 3 cycles, but ESP value is available
;; earlier
(define_insn_reservation "athlon_push" 2
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "push"))
"athlon-direct,athlon-agu,athlon-store")
(define_insn_reservation "athlon_pop" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "pop"))
"athlon-vector,athlon-load,athlon-ieu")
(define_insn_reservation "athlon_pop_k8" 3
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "pop"))
"athlon-double,(athlon-ieu+athlon-load)")
(define_insn_reservation "athlon_pop_amdfam10" 3
@ -186,13 +186,13 @@
(eq_attr "type" "leave"))
"athlon-vector,(athlon-ieu+athlon-load)")
(define_insn_reservation "athlon_leave_k8" 3
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(eq_attr "type" "leave"))
"athlon-double,(athlon-ieu+athlon-load)")
;; Lea executes in AGU unit with 2 cycles latency.
(define_insn_reservation "athlon_lea" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "lea"))
"athlon-direct,athlon-agu,nothing")
;; Lea executes in AGU unit with 1 cycle latency on AMDFAM10
@ -209,13 +209,13 @@
"athlon-vector,athlon-ieu0,athlon-mult,nothing,nothing,athlon-ieu0")
;; ??? Widening multiply is vector or double.
(define_insn_reservation "athlon_imul_k8_DI" 4
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "imul")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "none,unknown"))))
"athlon-direct0,athlon-ieu0,athlon-mult,nothing,athlon-ieu0")
(define_insn_reservation "athlon_imul_k8" 3
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "imul")
(eq_attr "memory" "none,unknown")))
"athlon-direct0,athlon-ieu0,athlon-mult,athlon-ieu0")
@ -231,13 +231,13 @@
(eq_attr "memory" "load,both")))
"athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,nothing,athlon-ieu")
(define_insn_reservation "athlon_imul_mem_k8_DI" 7
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "imul")
(and (eq_attr "mode" "DI")
(eq_attr "memory" "load,both"))))
"athlon-vector,athlon-load,athlon-ieu,athlon-mult,nothing,athlon-ieu")
(define_insn_reservation "athlon_imul_mem_k8" 6
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "imul")
(eq_attr "memory" "load,both")))
"athlon-vector,athlon-load,athlon-ieu,athlon-mult,athlon-ieu")
@ -251,12 +251,12 @@
;; Using the same heuristics for amdfam10 as K8 with idiv
(define_insn_reservation "athlon_idiv" 6
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "none,unknown")))
"athlon-vector,(athlon-ieu0*6+(athlon-fpsched,athlon-fvector))")
(define_insn_reservation "athlon_idiv_mem" 9
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "idiv")
(eq_attr "memory" "load,both")))
"athlon-vector,((athlon-load,athlon-ieu0*6)+(athlon-fpsched,athlon-fvector))")
@ -264,13 +264,13 @@
;; as idiv to create smaller automata. This probably does not matter much.
;; Using the same heuristics for amdfam10 as K8 with idiv
(define_insn_reservation "athlon_str" 6
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "str")
(eq_attr "memory" "load,both,store")))
"athlon-vector,athlon-load,athlon-ieu0*6")
(define_insn_reservation "athlon_idirect" 1
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "direct")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "none,unknown"))))
@ -282,7 +282,7 @@
(eq_attr "memory" "none,unknown"))))
"athlon-direct,athlon-ieu")
(define_insn_reservation "athlon_ivector" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "none,unknown"))))
@ -295,13 +295,13 @@
"athlon-vector,athlon-ieu,athlon-ieu")
(define_insn_reservation "athlon_idirect_loadmov" 3
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "imov")
(eq_attr "memory" "load")))
"athlon-direct,athlon-load")
(define_insn_reservation "athlon_idirect_load" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "direct")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "load"))))
@ -313,7 +313,7 @@
(eq_attr "memory" "load"))))
"athlon-direct,athlon-load,athlon-ieu")
(define_insn_reservation "athlon_ivector_load" 6
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "load"))))
@ -326,13 +326,13 @@
"athlon-vector,athlon-load,athlon-ieu,athlon-ieu")
(define_insn_reservation "athlon_idirect_movstore" 1
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "imov")
(eq_attr "memory" "store")))
"athlon-direct,athlon-agu,athlon-store")
(define_insn_reservation "athlon_idirect_both" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "direct")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "both"))))
@ -349,7 +349,7 @@
athlon-store")
(define_insn_reservation "athlon_ivector_both" 6
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "both"))))
@ -368,7 +368,7 @@
athlon-store")
(define_insn_reservation "athlon_idirect_store" 1
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "direct")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "store"))))
@ -383,7 +383,7 @@
athlon-store")
(define_insn_reservation "athlon_ivector_store" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "unit" "integer,unknown")
(eq_attr "memory" "store"))))
@ -405,7 +405,7 @@
(eq_attr "mode" "XF"))))
"athlon-vector,athlon-fpload2,athlon-fvector*9")
(define_insn_reservation "athlon_fldxf_k8" 13
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fmov")
(and (eq_attr "memory" "load")
(eq_attr "mode" "XF"))))
@ -417,7 +417,7 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fany")
(define_insn_reservation "athlon_fld_k8" 2
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fmov")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fstore")
@ -429,7 +429,7 @@
(eq_attr "mode" "XF"))))
"athlon-vector,(athlon-fpsched+athlon-agu),(athlon-store2+(athlon-fvector*7))")
(define_insn_reservation "athlon_fstxf_k8" 8
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fmov")
(and (eq_attr "memory" "store,both")
(eq_attr "mode" "XF"))))
@ -440,16 +440,16 @@
(eq_attr "memory" "store,both")))
"athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
(define_insn_reservation "athlon_fst_k8" 2
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fmov")
(eq_attr "memory" "store,both")))
"athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
(define_insn_reservation "athlon_fist" 4
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fistp,fisttp"))
"athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
(define_insn_reservation "athlon_fmov" 2
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fmov"))
"athlon-direct,athlon-fpsched,athlon-faddmul")
(define_insn_reservation "athlon_fadd_load" 4
@ -458,12 +458,12 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_fadd_load_k8" 6
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fop")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_fadd" 4
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fop"))
"athlon-direct,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_fmul_load" 4
@ -472,16 +472,16 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fmul")
(define_insn_reservation "athlon_fmul_load_k8" 6
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fmul")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fmul")
(define_insn_reservation "athlon_fmul" 4
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fmul"))
"athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_fsgn" 2
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fsgn"))
"athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_fdiv_load" 24
@ -490,7 +490,7 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fmul")
(define_insn_reservation "athlon_fdiv_load_k8" 13
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fdiv")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fmul")
@ -499,16 +499,16 @@
(eq_attr "type" "fdiv"))
"athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_fdiv_k8" 11
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(eq_attr "type" "fdiv"))
"athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_fpspc_load" 103
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "fpspc")
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload,athlon-fvector")
(define_insn_reservation "athlon_fpspc" 100
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fpspc"))
"athlon-vector,athlon-fpsched,athlon-fvector")
(define_insn_reservation "athlon_fcmov_load" 7
@ -521,12 +521,12 @@
(eq_attr "type" "fcmov"))
"athlon-vector,athlon-fpsched,athlon-fvector")
(define_insn_reservation "athlon_fcmov_load_k8" 17
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fcmov")
(eq_attr "memory" "load")))
"athlon-vector,athlon-fploadk8,athlon-fvector")
(define_insn_reservation "athlon_fcmov_k8" 15
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(eq_attr "type" "fcmov"))
"athlon-vector,athlon-fpsched,athlon-fvector")
;; fcomi is vector decoded by uses only one pipe.
@ -537,13 +537,13 @@
(eq_attr "memory" "load"))))
"athlon-vector,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_fcomi_load_k8" 5
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fcmp")
(and (eq_attr "athlon_decode" "vector")
(eq_attr "memory" "load"))))
"athlon-vector,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_fcomi" 3
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "athlon_decode" "vector")
(eq_attr "type" "fcmp")))
"athlon-vector,athlon-fpsched,athlon-fadd")
@ -553,18 +553,18 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_fcom_load_k8" 4
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "fcmp")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_fcom" 2
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(eq_attr "type" "fcmp"))
"athlon-direct,athlon-fpsched,athlon-fadd")
;; Never seen by the scheduler because we still don't do post reg-stack
;; scheduling.
;(define_insn_reservation "athlon_fxch" 2
; (and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
; (and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
; (eq_attr "type" "fxch"))
; "athlon-direct,athlon-fpsched,athlon-fany")
@ -580,13 +580,13 @@
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand")))
"athlon-direct,athlon-fploadk8,athlon-fstore")
(define_insn_reservation "athlon_movsd_load_generic64" 2
(and (eq_attr "cpu" "generic64")
(define_insn_reservation "athlon_movsd_load_generic" 2
(and (eq_attr "cpu" "generic")
(and (eq_attr "type" "ssemov")
(match_operand:DF 1 "memory_operand")))
"athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)")
(define_insn_reservation "athlon_movaps_load_k8" 2
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssemov")
(and (eq_attr "mode" "V4SF,V2DF,TI")
(eq_attr "memory" "load"))))
@ -604,7 +604,7 @@
(eq_attr "memory" "load"))))
"athlon-vector,athlon-fpload,(athlon-fany*2)")
(define_insn_reservation "athlon_movss_load_k8" 1
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssemov")
(and (eq_attr "mode" "SF,DI")
(eq_attr "memory" "load"))))
@ -615,7 +615,7 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fany")
(define_insn_reservation "athlon_mmxsseld_k8" 2
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "mmxmov,ssemov")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fstore")
@ -637,19 +637,19 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8, athlon-fany")
(define_insn_reservation "athlon_mmxssest" 3
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "mmxmov,ssemov")
(and (eq_attr "mode" "V4SF,V2DF,TI")
(eq_attr "memory" "store,both"))))
"athlon-vector,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
(define_insn_reservation "athlon_mmxssest_k8" 3
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "mmxmov,ssemov")
(and (eq_attr "mode" "V4SF,V2DF,TI")
(eq_attr "memory" "store,both"))))
"athlon-double,(athlon-fpsched+athlon-agu),((athlon-fstore+athlon-store2)*2)")
(define_insn_reservation "athlon_mmxssest_short" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "mmxmov,ssemov")
(eq_attr "memory" "store,both")))
"athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
@ -673,7 +673,7 @@
(eq_attr "memory" "store,both")))
"athlon-direct,(athlon-fpsched+athlon-agu),(athlon-fstore+athlon-store)")
(define_insn_reservation "athlon_movaps_k8" 2
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssemov")
(eq_attr "mode" "V4SF,V2DF,TI")))
"athlon-double,athlon-fpsched,((athlon-faddmul+athlon-faddmul) | (athlon-faddmul, athlon-faddmul))")
@ -683,25 +683,25 @@
(eq_attr "mode" "V4SF,V2DF,TI")))
"athlon-vector,athlon-fpsched,(athlon-faddmul+athlon-faddmul)")
(define_insn_reservation "athlon_mmxssemov" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "mmxmov,ssemov"))
"athlon-direct,athlon-fpsched,athlon-faddmul")
(define_insn_reservation "athlon_mmxmul_load" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "mmxmul")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-fmul")
(define_insn_reservation "athlon_mmxmul" 3
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "mmxmul"))
"athlon-direct,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_mmx_load" 3
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "unit" "mmx")
(eq_attr "memory" "load")))
"athlon-direct,athlon-fpload,athlon-faddmul")
(define_insn_reservation "athlon_mmx" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "unit" "mmx"))
"athlon-direct,athlon-fpsched,athlon-faddmul")
;; SSE operations are handled by the i387 unit as well. The latency
@ -713,7 +713,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload2,(athlon-fmul*2)")
(define_insn_reservation "athlon_sselog_load_k8" 5
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
(eq_attr "memory" "load")))
"athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
@ -727,7 +727,7 @@
(eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
"athlon-vector,athlon-fpsched,athlon-fmul*2")
(define_insn_reservation "athlon_sselog_k8" 3
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1"))
"athlon-double,athlon-fpsched,athlon-fmul")
(define_insn_reservation "athlon_sselog_amdfam10" 2
@ -743,13 +743,13 @@
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_ssecmp_load_k8" 4
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "ssecmp")
(and (eq_attr "mode" "SF,DF,DI,TI")
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_ssecmp" 2
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "ssecmp")
(eq_attr "mode" "SF,DF,DI,TI")))
"athlon-direct,athlon-fpsched,athlon-fadd")
@ -759,7 +759,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload2,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector_load_k8" 5
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssecmp")
(eq_attr "memory" "load")))
"athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
@ -773,7 +773,7 @@
(eq_attr "type" "ssecmp"))
"athlon-vector,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector_k8" 3
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "ssecmp"))
"athlon-double,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_ssecmpvector_amdfam10" 2
@ -786,7 +786,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_ssecomi_load_k8" 6
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssecomi")
(eq_attr "memory" "load")))
"athlon-vector,athlon-fploadk8,athlon-fadd")
@ -796,7 +796,7 @@
(eq_attr "memory" "load")))
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_ssecomi" 4
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(eq_attr "type" "ssecomi"))
"athlon-vector,athlon-fpsched,athlon-fadd")
(define_insn_reservation "athlon_ssecomi_amdfam10" 3
@ -811,13 +811,13 @@
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fpload,athlon-fadd")
(define_insn_reservation "athlon_sseadd_load_k8" 6
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "sseadd,sseadd1")
(and (eq_attr "mode" "SF,DF,DI")
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fploadk8,athlon-fadd")
(define_insn_reservation "athlon_sseadd" 4
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "sseadd,sseadd1")
(eq_attr "mode" "SF,DF,DI")))
"athlon-direct,athlon-fpsched,athlon-fadd")
@ -827,7 +827,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload2,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector_load_k8" 7
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "sseadd,sseadd1")
(eq_attr "memory" "load")))
"athlon-double,athlon-fpload2k8,(athlon-fadd*2)")
@ -841,7 +841,7 @@
(eq_attr "type" "sseadd,sseadd1"))
"athlon-vector,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector_k8" 5
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "sseadd,sseadd1"))
"athlon-double,athlon-fpsched,(athlon-fadd*2)")
(define_insn_reservation "athlon_sseaddvector_amdfam10" 4
@ -855,7 +855,7 @@
;; cvtss2sd
(define_insn_reservation "athlon_ssecvt_cvtss2sd_load_k8" 4
(and (eq_attr "cpu" "k8,athlon,generic64")
(and (eq_attr "cpu" "k8,athlon,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "direct")
(and (eq_attr "mode" "DF")
@ -869,7 +869,7 @@
(eq_attr "memory" "load")))))
"athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
(define_insn_reservation "athlon_ssecvt_cvtss2sd" 2
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "direct")
(eq_attr "mode" "DF"))))
@ -882,7 +882,7 @@
"athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
;; cvtps2pd. Model same way the other double decoded FP conversions.
(define_insn_reservation "athlon_ssecvt_cvtps2pd_load_k8" 5
(and (eq_attr "cpu" "k8,athlon,generic64")
(and (eq_attr "cpu" "k8,athlon,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "double")
(and (eq_attr "mode" "V2DF,V4SF,TI")
@ -896,7 +896,7 @@
(eq_attr "memory" "load")))))
"athlon-direct,athlon-fploadk8,athlon-fstore")
(define_insn_reservation "athlon_ssecvt_cvtps2pd_k8" 3
(and (eq_attr "cpu" "k8,athlon,generic64")
(and (eq_attr "cpu" "k8,athlon,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "double")
(eq_attr "mode" "V2DF,V4SF,TI"))))
@ -932,7 +932,7 @@
(eq_attr "memory" "load")))))
"athlon-vector,athlon-fpload,(athlon-fstore*2)")
(define_insn_reservation "athlon_sseicvt_cvtsi2ss_load_k8" 9
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "sseicvt")
(and (eq_attr "athlon_decode" "double")
(and (eq_attr "mode" "SF,DF")
@ -947,7 +947,7 @@
"athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
;; cvtsi2sd reg,reg is double decoded (vector on Athlon)
(define_insn_reservation "athlon_sseicvt_cvtsi2sd_k8" 11
(and (eq_attr "cpu" "k8,athlon,generic64")
(and (eq_attr "cpu" "k8,athlon,generic")
(and (eq_attr "type" "sseicvt")
(and (eq_attr "athlon_decode" "double")
(and (eq_attr "mode" "SF,DF")
@ -962,7 +962,7 @@
"athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
;; cvtsi2ss reg, reg is doublepath
(define_insn_reservation "athlon_sseicvt_cvtsi2ss" 14
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "sseicvt")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "mode" "SF,DF")
@ -977,7 +977,7 @@
"athlon-vector,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
;; cvtsd2ss mem,reg is doublepath, troughput unknown, latency 9
(define_insn_reservation "athlon_ssecvt_cvtsd2ss_load_k8" 9
(and (eq_attr "cpu" "k8,athlon,generic64")
(and (eq_attr "cpu" "k8,athlon,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "double")
(and (eq_attr "mode" "SF")
@ -992,7 +992,7 @@
"athlon-double,athlon-fploadk8,(athlon-faddmul+athlon-fstore)")
;; cvtsd2ss reg,reg is vectorpath, troughput unknown, latency 12
(define_insn_reservation "athlon_ssecvt_cvtsd2ss" 12
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "mode" "SF")
@ -1006,7 +1006,7 @@
(eq_attr "memory" "none")))))
"athlon-vector,athlon-fpsched,athlon-faddmul,(athlon-fstore*2)")
(define_insn_reservation "athlon_ssecvt_cvtpd2ps_load_k8" 8
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "mode" "V4SF,V2DF,TI")
@ -1022,7 +1022,7 @@
;; cvtpd2ps mem,reg is vectorpath, troughput unknown, latency 10
;; ??? Why it is fater than cvtsd2ss?
(define_insn_reservation "athlon_ssecvt_cvtpd2ps" 8
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "ssecvt")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "mode" "V4SF,V2DF,TI")
@ -1037,7 +1037,7 @@
"athlon-double,athlon-fpsched,(athlon-faddmul+athlon-fstore)")
;; cvtsd2si mem,reg is doublepath, troughput 1, latency 9
(define_insn_reservation "athlon_secvt_cvtsX2si_load" 9
(and (eq_attr "cpu" "athlon,k8,generic64")
(and (eq_attr "cpu" "athlon,k8,generic")
(and (eq_attr "type" "sseicvt")
(and (eq_attr "athlon_decode" "vector")
(and (eq_attr "mode" "SI,DI")
@ -1059,7 +1059,7 @@
(eq_attr "memory" "none")))))
"athlon-vector,athlon-fpsched,athlon-fvector")
(define_insn_reservation "athlon_ssecvt_cvtsX2si_k8" 9
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "sseicvt")
(and (eq_attr "athlon_decode" "double")
(and (eq_attr "mode" "SI,DI")
@ -1097,13 +1097,13 @@
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fpload,athlon-fmul")
(define_insn_reservation "athlon_ssemul_load_k8" 6
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "ssemul")
(and (eq_attr "mode" "SF,DF")
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fploadk8,athlon-fmul")
(define_insn_reservation "athlon_ssemul" 4
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "ssemul")
(eq_attr "mode" "SF,DF")))
"athlon-direct,athlon-fpsched,athlon-fmul")
@ -1113,7 +1113,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload2,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector_load_k8" 7
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssemul")
(eq_attr "memory" "load")))
"athlon-double,athlon-fpload2k8,(athlon-fmul*2)")
@ -1127,7 +1127,7 @@
(eq_attr "type" "ssemul"))
"athlon-vector,athlon-fpsched,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector_k8" 5
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "ssemul"))
"athlon-double,athlon-fpsched,(athlon-fmul*2)")
(define_insn_reservation "athlon_ssemulvector_amdfam10" 4
@ -1142,13 +1142,13 @@
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fpload,athlon-fmul*17")
(define_insn_reservation "athlon_ssediv_load_k8" 22
(and (eq_attr "cpu" "k8,generic64,amdfam10")
(and (eq_attr "cpu" "k8,generic,amdfam10")
(and (eq_attr "type" "ssediv")
(and (eq_attr "mode" "SF,DF")
(eq_attr "memory" "load"))))
"athlon-direct,athlon-fploadk8,athlon-fmul*17")
(define_insn_reservation "athlon_ssediv" 20
(and (eq_attr "cpu" "athlon,k8,generic64,amdfam10")
(and (eq_attr "cpu" "athlon,k8,generic,amdfam10")
(and (eq_attr "type" "ssediv")
(eq_attr "mode" "SF,DF")))
"athlon-direct,athlon-fpsched,athlon-fmul*17")
@ -1158,7 +1158,7 @@
(eq_attr "memory" "load")))
"athlon-vector,athlon-fpload2,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector_load_k8" 35
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(and (eq_attr "type" "ssediv")
(eq_attr "memory" "load")))
"athlon-double,athlon-fpload2k8,athlon-fmul*34")
@ -1172,7 +1172,7 @@
(eq_attr "type" "ssediv"))
"athlon-vector,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector_k8" 39
(and (eq_attr "cpu" "k8,generic64")
(and (eq_attr "cpu" "k8,generic")
(eq_attr "type" "ssediv"))
"athlon-double,athlon-fmul*34")
(define_insn_reservation "athlon_ssedivvector_amdfam10" 20

10
gcc/config/i386/driver-i386.c
View File

@ -578,13 +578,13 @@ const char *host_detect_local_cpu (int argc, const char **argv)
case 6:
if (model > 9)
/* Use the default detection procedure. */
processor = PROCESSOR_GENERIC32;
processor = PROCESSOR_GENERIC;
else if (model == 9)
cpu = "c3-2";
else if (model >= 6)
cpu = "c3";
else
processor = PROCESSOR_GENERIC32;
processor = PROCESSOR_GENERIC;
break;
case 5:
if (has_3dnow)
@ -592,11 +592,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
else if (has_mmx)
cpu = "winchip2-c6";
else
processor = PROCESSOR_GENERIC32;
processor = PROCESSOR_GENERIC;
break;
default:
/* We have no idea. */
processor = PROCESSOR_GENERIC32;
processor = PROCESSOR_GENERIC;
}
}
}
@ -618,7 +618,7 @@ const char *host_detect_local_cpu (int argc, const char **argv)
break;
default:
/* We have no idea. */
processor = PROCESSOR_GENERIC32;
processor = PROCESSOR_GENERIC;
}
}

6
gcc/config/i386/i386-c.c
View File

@ -156,8 +156,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
case PROCESSOR_GENERIC:
gcc_unreachable ();
}
@ -248,8 +247,7 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_SLM:
def_or_undef (parse_in, "__tune_slm__");
break;
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
case PROCESSOR_GENERIC:
break;
/* use PROCESSOR_max to not set/unset the tune macro. */
case PROCESSOR_max:

141
gcc/config/i386/i386.c
View File

@ -1644,18 +1644,19 @@ struct processor_costs slm_cost = {
1, /* cond_not_taken_branch_cost. */
};
/* Generic64 should produce code tuned for Nocona and K8. */
/* Generic should produce code tuned for Core-i7 (and newer chips)
and btver1 (and newer chips). */
static stringop_algs generic64_memcpy[2] = {
static stringop_algs generic_memcpy[2] = {
DUMMY_STRINGOP_ALGS,
{libcall, {{32, loop, false}, {8192, rep_prefix_8_byte, false},
{-1, libcall, false}}}};
static stringop_algs generic64_memset[2] = {
static stringop_algs generic_memset[2] = {
DUMMY_STRINGOP_ALGS,
{libcall, {{32, loop, false}, {8192, rep_prefix_8_byte, false},
{-1, libcall, false}}}};
static const
struct processor_costs generic64_cost = {
struct processor_costs generic_cost = {
COSTS_N_INSNS (1), /* cost of an add instruction */
/* On all chips taken into consideration lea is 2 cycles and more. With
this cost however our current implementation of synth_mult results in
@ -1713,8 +1714,8 @@ struct processor_costs generic64_cost = {
COSTS_N_INSNS (8), /* cost of FABS instruction. */
COSTS_N_INSNS (8), /* cost of FCHS instruction. */
COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
generic64_memcpy,
generic64_memset,
generic_memcpy,
generic_memset,
1, /* scalar_stmt_cost. */
1, /* scalar load_cost. */
1, /* scalar_store_cost. */
@ -1814,83 +1815,6 @@ struct processor_costs core_cost = {
1, /* cond_not_taken_branch_cost. */
};
/* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
Athlon and K8. */
static stringop_algs generic32_memcpy[2] = {
{libcall, {{32, loop, false}, {8192, rep_prefix_4_byte, false},
{-1, libcall, false}}},
DUMMY_STRINGOP_ALGS};
static stringop_algs generic32_memset[2] = {
{libcall, {{32, loop, false}, {8192, rep_prefix_4_byte, false},
{-1, libcall, false}}},
DUMMY_STRINGOP_ALGS};
static const
struct processor_costs generic32_cost = {
COSTS_N_INSNS (1), /* cost of an add instruction */
COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
COSTS_N_INSNS (1), /* variable shift costs */
COSTS_N_INSNS (1), /* constant shift costs */
{COSTS_N_INSNS (3), /* cost of starting multiply for QI */
COSTS_N_INSNS (4), /* HI */
COSTS_N_INSNS (3), /* SI */
COSTS_N_INSNS (4), /* DI */
COSTS_N_INSNS (2)}, /* other */
0, /* cost of multiply per each bit set */
{COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
COSTS_N_INSNS (26), /* HI */
COSTS_N_INSNS (42), /* SI */
COSTS_N_INSNS (74), /* DI */
COSTS_N_INSNS (74)}, /* other */
COSTS_N_INSNS (1), /* cost of movsx */
COSTS_N_INSNS (1), /* cost of movzx */
8, /* "large" insn */
17, /* MOVE_RATIO */
4, /* cost for loading QImode using movzbl */
{4, 4, 4}, /* cost of loading integer registers
in QImode, HImode and SImode.
Relative to reg-reg move (2). */
{4, 4, 4}, /* cost of storing integer registers */
4, /* cost of reg,reg fld/fst */
{12, 12, 12}, /* cost of loading fp registers
in SFmode, DFmode and XFmode */
{6, 6, 8}, /* cost of storing fp registers
in SFmode, DFmode and XFmode */
2, /* cost of moving MMX register */
{8, 8}, /* cost of loading MMX registers
in SImode and DImode */
{8, 8}, /* cost of storing MMX registers
in SImode and DImode */
2, /* cost of moving SSE register */
{8, 8, 8}, /* cost of loading SSE registers
in SImode, DImode and TImode */
{8, 8, 8}, /* cost of storing SSE registers
in SImode, DImode and TImode */
5, /* MMX or SSE register to integer */
32, /* size of l1 cache. */
256, /* size of l2 cache. */
64, /* size of prefetch block */
6, /* number of parallel prefetches */
3, /* Branch cost */
COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
COSTS_N_INSNS (8), /* cost of FMUL instruction. */
COSTS_N_INSNS (20), /* cost of FDIV instruction. */
COSTS_N_INSNS (8), /* cost of FABS instruction. */
COSTS_N_INSNS (8), /* cost of FCHS instruction. */
COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
generic32_memcpy,
generic32_memset,
1, /* scalar_stmt_cost. */
1, /* scalar load_cost. */
1, /* scalar_store_cost. */
1, /* vec_stmt_cost. */
1, /* vec_to_scalar_cost. */
1, /* scalar_to_vec_cost. */
1, /* vec_align_load_cost. */
2, /* vec_unalign_load_cost. */
1, /* vec_store_cost. */
3, /* cond_taken_branch_cost. */
1, /* cond_not_taken_branch_cost. */
};
/* Set by -mtune. */
const struct processor_costs *ix86_tune_cost = &pentium_cost;
@ -1929,12 +1853,7 @@ const struct processor_costs *ix86_cost = &pentium_cost;
#define m_BTVER (m_BTVER1 | m_BTVER2)
#define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
#define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
#define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
/* Generic instruction choice should be common subset of supported CPUs
(PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
#define m_GENERIC (m_GENERIC32 | m_GENERIC64)
#define m_GENERIC (1<<PROCESSOR_GENERIC)
const char* ix86_tune_feature_names[X86_TUNE_LAST] = {
#undef DEF_TUNE
@ -2384,8 +2303,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{&core_cost, 16, 10, 16, 10, 16},
/* Core avx2 */
{&core_cost, 16, 10, 16, 10, 16},
{&generic32_cost, 16, 7, 16, 7, 16},
{&generic64_cost, 16, 10, 16, 10, 16},
{&generic_cost, 16, 10, 16, 10, 16},
{&amdfam10_cost, 32, 24, 32, 7, 32},
{&bdver1_cost, 16, 10, 16, 7, 11},
{&bdver2_cost, 16, 10, 16, 7, 11},
@ -3182,7 +3100,7 @@ ix86_option_override_internal (bool main_args_p)
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
| PTA_XSAVEOPT | PTA_FSGSBASE},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC64,
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE},
@ -3193,9 +3111,7 @@ ix86_option_override_internal (bool main_args_p)
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
{"generic32", PROCESSOR_GENERIC32, CPU_PENTIUMPRO,
PTA_HLE /* flags are only used for -march switch. */ },
{"generic64", PROCESSOR_GENERIC64, CPU_GENERIC64,
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
PTA_64BIT
| PTA_HLE /* flags are only used for -march switch. */ },
};
@ -3295,16 +3211,12 @@ ix86_option_override_internal (bool main_args_p)
-mtune=native, as it was changed by the driver. */
|| !strcmp (ix86_tune_string, "native"))
{
if (TARGET_64BIT)
ix86_tune_string = "generic64";
else
ix86_tune_string = "generic32";
ix86_tune_string = "generic";
}
/* If this call is for setting the option attribute, allow the
generic32/generic64 that was previously set. */
generic that was previously set. */
else if (!main_args_p
&& (!strcmp (ix86_tune_string, "generic32")
|| !strcmp (ix86_tune_string, "generic64")))
&& !strcmp (ix86_tune_string, "generic"))
;
else if (!strncmp (ix86_tune_string, "generic", 7))
error ("bad value (%s) for %stune=%s %s",
@ -3330,10 +3242,7 @@ ix86_option_override_internal (bool main_args_p)
|| !strcmp (ix86_tune_string, "x86-64")
|| !strcmp (ix86_tune_string, "i686"))
{
if (TARGET_64BIT)
ix86_tune_string = "generic64";
else
ix86_tune_string = "generic32";
ix86_tune_string = "generic";
}
}
@ -3630,20 +3539,6 @@ ix86_option_override_internal (bool main_args_p)
"instruction set");
}
}
else
{
/* Adjust tuning when compiling for 32-bit ABI. */
switch (ix86_tune)
{
case PROCESSOR_GENERIC64:
ix86_tune = PROCESSOR_GENERIC32;
ix86_schedule = CPU_PENTIUMPRO;
break;
default:
break;
}
}
/* Intel CPUs have always interpreted SSE prefetch instructions as
NOPs; so, we can enable SSE prefetch instructions even when
-mtune (rather than -march) points us to a processor that has them.
@ -24503,8 +24398,7 @@ ix86_issue_rate (void)
case PROCESSOR_K8:
case PROCESSOR_AMDFAM10:
case PROCESSOR_NOCONA:
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
case PROCESSOR_GENERIC:
case PROCESSOR_BDVER1:
case PROCESSOR_BDVER2:
case PROCESSOR_BDVER3:
@ -24768,8 +24662,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case PROCESSOR_BTVER1:
case PROCESSOR_BTVER2:
case PROCESSOR_ATOM:
case PROCESSOR_GENERIC32:
case PROCESSOR_GENERIC64:
case PROCESSOR_GENERIC:
memory = get_attr_memory (insn);
/* Show ability of reorder buffer to hide latency of load by executing

7
gcc/config/i386/i386.h
View File

@ -251,9 +251,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)
#define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7)
#define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL)
#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)
#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
#define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1)
#define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2)
@ -2141,8 +2139,7 @@ enum processor_type
PROCESSOR_CORE2,
PROCESSOR_COREI7,
PROCESSOR_HASWELL,
PROCESSOR_GENERIC32,
PROCESSOR_GENERIC64,
PROCESSOR_GENERIC,
PROCESSOR_AMDFAM10,
PROCESSOR_BDVER1,
PROCESSOR_BDVER2,

2
gcc/config/i386/i386.md
View File

@ -349,7 +349,7 @@
;; Processor type.
(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
atom,slm,generic64,amdfam10,bdver1,bdver2,bdver3,btver1,btver2"
atom,slm,generic,amdfam10,bdver1,bdver2,bdver3,btver1,btver2"
(const (symbol_ref "ix86_schedule")))
;; A basic instruction type. Refinements due to arguments to be

13
gcc/config/i386/x86-tune.def
View File

@ -23,7 +23,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
tradeoff. We can't enable it for 32bit generic because it does not
work well with PPro base chips. */
DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC64)
m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_GENERIC)
DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
| m_GENERIC)
@ -49,10 +49,7 @@ DEF_TUNE (X86_TUNE_MOVX, "movx",
register stalls on Generic32 compilation setting as well. However
in current implementation the partial register stalls are not eliminated
very well - they can be introduced via subregs synthesized by combine
and can happen in caller/callee saving sequences. Because this option
pays back little on PPro based chips and is in conflict with partial reg
dependencies used by Athlon/P4 based chips, it is better to leave it off
for generic32 for now. */
and can happen in caller/callee saving sequences. */
DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
m_CORE_ALL | m_GENERIC)
@ -163,7 +160,7 @@ DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_SLM | m_K6_GEODE
| m_ATHLON_K8 | m_GENERIC)
DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
m_CORE_ALL | m_K8 | m_GENERIC64)
m_CORE_ALL | m_K8 | m_GENERIC)
/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
and SImode multiply, but 386 and 486 do HImode multiply faster. */
DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
@ -171,11 +168,11 @@ DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
vector path on AMD machines. */
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC64)
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
machines. */
DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC64)
m_CORE_ALL | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC)
/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
than a MOV. */
DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT)