PR target/11607 and PR target/11516
PR target/11607 and PR target/11516 * pa.md (extzv, extv, insv): Revert latter half of last patch. From-SVN: r69707
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@ -1,3 +1,8 @@
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2003-07-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
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PR target/11607 and PR target/11516
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* pa.md (extzv, extv, insv): Revert latter half of last patch.
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2003-07-22 Mark Mitchell <mark@codesourcery.com>
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* fold-const.c (force_fit_type): Handle OFFSET_TYPE.
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@ -7158,17 +7158,12 @@
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FAIL;
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if (TARGET_64BIT)
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
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FAIL;
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emit_insn (gen_extzv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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}
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else
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
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if (! uint5_operand (operands[2], SImode)
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|| ! uint5_operand (operands[3], SImode))
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FAIL;
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emit_insn (gen_extzv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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@ -7179,8 +7174,8 @@
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(define_insn "extzv_32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "uint32_operand" "")
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(match_operand:SI 3 "uint32_operand" "")))]
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"{extru|extrw,u} %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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@ -7229,17 +7224,12 @@
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FAIL;
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if (TARGET_64BIT)
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
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FAIL;
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emit_insn (gen_extv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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}
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else
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
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if (! uint5_operand (operands[2], SImode)
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|| ! uint5_operand (operands[3], SImode))
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FAIL;
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emit_insn (gen_extv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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@ -7250,8 +7240,8 @@
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(define_insn "extv_32"
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[(set (match_operand:SI 0 "register_operand" "=r")
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(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand:SI 2 "uint32_operand" "")
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(match_operand:SI 3 "uint32_operand" "")))]
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(match_operand:SI 2 "uint5_operand" "")
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(match_operand:SI 3 "uint5_operand" "")))]
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""
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"{extrs|extrw,s} %1,%3+%2-1,%2,%0"
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[(set_attr "type" "shift")
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@ -7297,17 +7287,12 @@
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"
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{
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if (TARGET_64BIT)
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
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FAIL;
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emit_insn (gen_insv_64 (operands[0], operands[1],
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operands[2], operands[3]));
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}
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else
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{
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if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
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|| (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
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if (! uint5_operand (operands[2], SImode)
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|| ! uint5_operand (operands[3], SImode))
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FAIL;
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emit_insn (gen_insv_32 (operands[0], operands[1],
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operands[2], operands[3]));
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@ -7317,8 +7302,8 @@
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(define_insn "insv_32"
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[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
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(match_operand:SI 1 "uint32_operand" "")
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(match_operand:SI 2 "uint32_operand" ""))
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(match_operand:SI 1 "uint5_operand" "")
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(match_operand:SI 2 "uint5_operand" ""))
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(match_operand:SI 3 "arith5_operand" "r,L"))]
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""
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"@
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