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re PR target/77270 (Flag -mprftchw is shared with 3dnow for -march=k8) 

PR target/77270
	* config/i386/i386.c (ix86_option_override_internal): Remove
	PTA_PRFCHW from entries that also have PTA_3DNOW flag.
	Enable SSE prefetch also for TARGET_PREFETCHWT1.
	Do not try to enable TARGET_PRFCHW ISA flag here.
	* config/i386/i386.md (prefetch): Enable also for TARGET_3DNOW.
	Rewrite expander function body.
	(*prefetch_3dnow): Enable for TARGET_3DNOW and TARGET_PREFETCHWT1.

From-SVN: r239626
This commit is contained in:
Uros Bizjak 2016-08-19 20:14:03 +02:00 committed by Uros Bizjak
parent c65699efcc
commit 9db4c25d2c
3 changed files with 58 additions and 34 deletions
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11
gcc/ChangeLog
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@ -1,3 +1,14 @@
2016-08-19 Uros Bizjak <ubizjak@gmail.com>
PR target/77270
* config/i386/i386.c (ix86_option_override_internal): Remove
PTA_PRFCHW from entries that also have PTA_3DNOW flag.
Enable SSE prefetch also for TARGET_PREFETCHWT1.
Do not try to enable TARGET_PRFCHW ISA flag here.
* config/i386/i386.md (prefetch): Enable also for TARGET_3DNOW.
Rewrite expander function body.
(*prefetch_3dnow): Enable for TARGET_3DNOW and TARGET_PREFETCHWT1.
2016-08-19 Joseph Myers <joseph@codesourcery.com>
PR c/32187

50
gcc/config/i386/i386.c
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@ -4843,9 +4843,9 @@ ix86_option_override_internal (bool main_args_p,
{"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
{"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
{"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
{"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
{"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
{"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
PTA_MMX | PTA_SSE | PTA_FXSR},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
@ -4896,20 +4896,20 @@ ix86_option_override_internal (bool main_args_p,
{"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
{"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
{"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
{"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW | PTA_PRFCHW},
{"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
{"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE | PTA_PRFCHW},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_PRFCHW | PTA_FXSR},
PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
{"x86-64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"eden-x2", PROCESSOR_K8, CPU_K8,
@ -4937,31 +4937,31 @@ ix86_option_override_internal (bool main_args_p,
| PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
{"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
{"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
| PTA_SSE2 | PTA_NO_SAHF | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_FXSR},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
| PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_FXSR},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@ -5668,14 +5668,10 @@ ix86_option_override_internal (bool main_args_p,
/* Enable SSE prefetch. */
if (TARGET_SSE_P (opts->x_ix86_isa_flags)
|| (TARGET_PRFCHW && !TARGET_3DNOW_P (opts->x_ix86_isa_flags)))
x86_prefetch_sse = true;
/* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
if (TARGET_3DNOW_P (opts->x_ix86_isa_flags)
|| (TARGET_PRFCHW_P (opts->x_ix86_isa_flags)
&& !TARGET_3DNOW_P (opts->x_ix86_isa_flags))
|| TARGET_PREFETCHWT1_P (opts->x_ix86_isa_flags))
opts->x_ix86_isa_flags
|= OPTION_MASK_ISA_PRFCHW & ~opts->x_ix86_isa_flags_explicit;
x86_prefetch_sse = true;
/* Enable popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2_P (opts->x_ix86_isa_flags)

31
gcc/config/i386/i386.md
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@ -18626,7 +18626,7 @@
[(prefetch (match_operand 0 "address_operand")
(match_operand:SI 1 "const_int_operand")
(match_operand:SI 2 "const_int_operand"))]
"TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1"
"TARGET_3DNOW || TARGET_PREFETCH_SSE || TARGET_PRFCHW || TARGET_PREFETCHWT1"
{
bool write = INTVAL (operands[1]) != 0;
int locality = INTVAL (operands[2]);
@ -18637,12 +18637,29 @@
supported by SSE counterpart or the SSE prefetch is not available
(K6 machines). Otherwise use SSE prefetch as it allows specifying
of locality. */
if (TARGET_PREFETCHWT1 && write && locality <= 2)
operands[2] = const2_rtx;
else if (TARGET_PRFCHW && (write || !TARGET_PREFETCH_SSE))
operands[2] = GEN_INT (3);
if (write)
{
if (TARGET_PREFETCHWT1)
operands[2] = GEN_INT (MAX (locality, 2));
else if (TARGET_3DNOW || TARGET_PRFCHW)
operands[2] = GEN_INT (3);
else
{
gcc_assert (TARGET_PREFETCH_SSE);
operands[1] = const0_rtx;
}
}
else
operands[1] = const0_rtx;
{
if (TARGET_PREFETCH_SSE)
;
else
{
gcc_assert (TARGET_3DNOW);
operands[2] = GEN_INT (3);
}
}
})
(define_insn "*prefetch_sse"
@ -18670,7 +18687,7 @@
[(prefetch (match_operand 0 "address_operand" "p")
(match_operand:SI 1 "const_int_operand" "n")
(const_int 3))]
"TARGET_PRFCHW"
"TARGET_3DNOW || TARGET_PRFCHW || TARGET_PREFETCHWT1"
{
if (INTVAL (operands[1]) == 0)
return "prefetch\t%a0";