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backport: tilegx.md (insn_v1mulu): Fix constraints on input operands. 

Backport from mainline:
	2013-03-27  Walter Lee  <walt@tilera.com>

	* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
	input operands.
	(insn_v1mulus): Ditto.
	(insn_v2muls): Ditto.

From-SVN: r197148
This commit is contained in:
Walter Lee 2013-03-27 06:37:39 +00:00 committed by Walter Lee
parent a72f3ab148
commit 9dc3f9d2ea
2 changed files with 16 additions and 6 deletions
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10
gcc/ChangeLog
View File

@ -1,3 +1,13 @@
2013-03-27 Walter Lee <walt@tilera.com>
Backport from mainline:
2013-03-27 Walter Lee <walt@tilera.com>
* config/tilegx/tilegx.md (insn_v1mulu): Fix constraints on
input operands.
(insn_v1mulus): Ditto.
(insn_v2muls): Ditto.
2013-03-27 Walter Lee <walt@tilera.com>
Backport from mainline:

12
gcc/config/tilegx/tilegx.md
View File

@ -4508,8 +4508,8 @@
(define_expand "insn_v1mulu"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_0_operand" "")]
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")]
""
{
tilegx_expand_builtin_vector_binop (gen_vec_widen_umult_lo_v8qi, V4HImode,
@ -4538,8 +4538,8 @@
(define_expand "insn_v1mulus"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_0_operand" "")]
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")]
""
{
tilegx_expand_builtin_vector_binop (gen_vec_widen_usmult_lo_v8qi, V4HImode,
@ -4566,8 +4566,8 @@
(define_expand "insn_v2muls"
[(match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "reg_or_0_operand" "")
(match_operand:DI 2 "reg_or_0_operand" "")]
(match_operand:DI 1 "register_operand" "")
(match_operand:DI 2 "register_operand" "")]
""
{
tilegx_expand_builtin_vector_binop (gen_vec_widen_smult_lo_v4qi, V2SImode,