re PR target/69100 (ICE in final_scan_insn with -msoft-float and __builtin_apply)
PR target/69100 * config/sparc/sparc.h (FUNCTION_ARG_REGNO_P): Return true in 64-bit mode for %f0-%f31 only if TARGET_FPU. From-SVN: r232050
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@ -1,3 +1,9 @@
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2016-01-04 Eric Botcazou <ebotcazou@adacore.com>
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PR target/69100
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* config/sparc/sparc.h (FUNCTION_ARG_REGNO_P): Return true in 64-bit
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mode for %f0-%f31 only if TARGET_FPU.
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2016-01-04 Eric Botcazou <ebotcazou@adacore.com>
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PR target/69072
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@ -1176,9 +1176,8 @@ extern char leaf_reg_remap[];
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On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
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#define FUNCTION_ARG_REGNO_P(N) \
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(TARGET_ARCH64 \
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? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
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: ((N) >= 8 && (N) <= 13))
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(((N) >= 8 && (N) <= 13) \
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|| (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63))
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/* Define a data type for recording info about an argument list
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during the scan of that argument list. This data type should
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@ -1,3 +1,7 @@
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2016-01-04 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.target/sparc/20160104-2.c: New test.
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2016-01-04 Eric Botcazou <ebotcazou@adacore.com>
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* gcc.target/sparc/20160104-1.c: New test.
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11
gcc/testsuite/gcc.target/sparc/20160104-2.c
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11
gcc/testsuite/gcc.target/sparc/20160104-2.c
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@ -0,0 +1,11 @@
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/* PR target/69100 */
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/* Reported by Zdenek Sojka <zsojka@seznam.cz> */
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/* { dg-do compile } */
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/* { dg-options "-mno-fpu" } */
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void
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foo (void)
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{
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__builtin_apply (0, 0, 0);
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}
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