* config/i386/i386.md (divmod<mode>4) Macroize expander from
divmoddi4, divmodsi4 and divmodhi4 patterns using SWI248 macro. (*divmod<mode>4): Macroize insn_and_split pattern from *divmoddi4_cltd_rex64, *divmodsi4_cltd and divmodhi4 insn patterns and their corresponding splitters usign SWI248 macro. Split SImode insn to generate cltd and DImode insn to generate cqto instead of move+shift when optimizing for size or TARGET_USE_CLTD is in effect. (*divmoddi4_nocltd_rex64, *divmodsi4_nocltd): Remove insn patterns. (*divmod<mode>4_noext): Macroize insn from *divmoddi_noext_rex64 and *divmodsi_noext patterns using SWI248 macro. (udivmod<mode>4): Macroize expander from udivmoddi4, udivmodsi4 and udivmodhi4 patterns using SWI248 macro. (*udivmod<mode>4): Macroize insn_and_split pattern from *udivmoddi4, udivmodsi4 and udivmodhi4 patterns and their corresponding splitters using SWI248 macro. (*udivmod<mode>4_noext): Macroize insn from *udivmoddi4_noext, *udivmodsi4_noext and *udivmodhi_noext patterns using SWI248 macro. From-SVN: r152416
This commit is contained in:
Uros Bizjak
parent
c2ce8cdc82
commit
9e51149de6
@ -1,3 +1,23 @@
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2009-10-02 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (divmod<mode>4) Macroize expander from
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divmoddi4, divmodsi4 and divmodhi4 patterns using SWI248 macro.
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(*divmod<mode>4): Macroize insn_and_split pattern from
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*divmoddi4_cltd_rex64, *divmodsi4_cltd and divmodhi4 insn patterns
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and their corresponding splitters usign SWI248 macro. Split SImode
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insn to generate cltd and DImode insn to generate cqto instead of
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move+shift when optimizing for size or TARGET_USE_CLTD is in effect.
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(*divmoddi4_nocltd_rex64, *divmodsi4_nocltd): Remove insn patterns.
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(*divmod<mode>4_noext): Macroize insn from *divmoddi_noext_rex64 and
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*divmodsi_noext patterns using SWI248 macro.
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(udivmod<mode>4): Macroize expander from udivmoddi4, udivmodsi4 and
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udivmodhi4 patterns using SWI248 macro.
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(*udivmod<mode>4): Macroize insn_and_split pattern from
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*udivmoddi4, udivmodsi4 and udivmodhi4 patterns and their
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corresponding splitters using SWI248 macro.
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(*udivmod<mode>4_noext): Macroize insn from *udivmoddi4_noext,
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*udivmodsi4_noext and *udivmodhi_noext patterns using SWI248 macro.
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2009-10-02 Eric Botcazou <ebotcazou@adacore.com>
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2009-10-02 Eric Botcazou <ebotcazou@adacore.com>
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* stor-layout.c (layout_type) <ARRAY_TYPE>: Make sure that an array
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* stor-layout.c (layout_type) <ARRAY_TYPE>: Make sure that an array
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@ -8916,296 +8916,111 @@
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}
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}
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})
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})
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;; Remainder instructions.
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;; Divmod instructions.
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(define_expand "divmoddi4"
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(define_expand "divmod<mode>4"
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[(parallel [(set (match_operand:DI 0 "register_operand" "")
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[(parallel [(set (match_operand:SWI248 0 "register_operand" "")
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(div:DI (match_operand:DI 1 "register_operand" "")
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(div:SWI248
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(match_operand:DI 2 "nonimmediate_operand" "")))
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(match_operand:SWI248 1 "register_operand" "")
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(set (match_operand:DI 3 "register_operand" "")
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(match_operand:SWI248 2 "nonimmediate_operand" "")))
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(mod:DI (match_dup 1) (match_dup 2)))
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(set (match_operand:SWI248 3 "register_operand" "")
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(mod:SWI248 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_64BIT"
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"(<MODE>mode != HImode) || TARGET_HIMODE_MATH"
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"")
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"")
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;; Allow to come the parameter in eax or edx to avoid extra moves.
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(define_insn_and_split "*divmod<mode>4"
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;; Penalize eax case slightly because it results in worse scheduling
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[(set (match_operand:SWI248 0 "register_operand" "=a")
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;; of code.
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(div:SWI248 (match_operand:SWI248 2 "register_operand" "0")
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(define_insn "*divmoddi4_nocltd_rex64"
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(match_operand:SWI248 3 "nonimmediate_operand" "rm")))
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[(set (match_operand:DI 0 "register_operand" "=&a,?a")
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(set (match_operand:SWI248 1 "register_operand" "=&d")
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(div:DI (match_operand:DI 2 "register_operand" "1,0")
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(mod:SWI248 (match_dup 2) (match_dup 3)))
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(match_operand:DI 3 "nonimmediate_operand" "rm,rm")))
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(set (match_operand:DI 1 "register_operand" "=&d,&d")
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(mod:DI (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
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"(<MODE>mode != HImode) || TARGET_HIMODE_MATH"
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"#"
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"#"
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[(set_attr "type" "multi")])
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"&& reload_completed"
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[(parallel [(set (match_dup 1)
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(define_insn "*divmoddi4_cltd_rex64"
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(ashiftrt:SWI248 (match_dup 4) (match_dup 5)))
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[(set (match_operand:DI 0 "register_operand" "=a")
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(div:DI (match_operand:DI 2 "register_operand" "a")
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(match_operand:DI 3 "nonimmediate_operand" "rm")))
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(set (match_operand:DI 1 "register_operand" "=&d")
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(mod:DI (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)"
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"#"
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[(set_attr "type" "multi")])
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(define_insn "*divmoddi_noext_rex64"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(div:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(set (match_operand:DI 3 "register_operand" "=d")
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(mod:DI (match_dup 1) (match_dup 2)))
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(use (match_operand:DI 4 "register_operand" "3"))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"idiv{q}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "DI")])
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(define_split
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[(set (match_operand:DI 0 "register_operand" "")
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(div:DI (match_operand:DI 1 "register_operand" "")
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(match_operand:DI 2 "nonimmediate_operand" "")))
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(set (match_operand:DI 3 "register_operand" "")
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(mod:DI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT && reload_completed"
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[(parallel [(set (match_dup 3)
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(ashiftrt:DI (match_dup 4) (const_int 63)))
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(clobber (reg:CC FLAGS_REG))])
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 0)
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(parallel [(set (match_dup 0)
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(div:DI (reg:DI 0) (match_dup 2)))
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(div:SWI248 (match_dup 2) (match_dup 3)))
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(set (match_dup 3)
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(set (match_dup 1)
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(mod:DI (reg:DI 0) (match_dup 2)))
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(mod:SWI248 (match_dup 2) (match_dup 3)))
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(use (match_dup 3))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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(clobber (reg:CC FLAGS_REG))])]
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{
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{
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operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
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if (<MODE>mode != HImode
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&& (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD))
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operands[4] = operands[2];
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else
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{
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/* Avoid use of cltd in favor of a mov+shift. */
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/* Avoid use of cltd in favor of a mov+shift. */
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if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
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emit_move_insn (operands[1], operands[2]);
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{
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if (true_regnum (operands[1]))
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emit_move_insn (operands[0], operands[1]);
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else
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emit_move_insn (operands[3], operands[1]);
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operands[4] = operands[3];
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}
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else
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{
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gcc_assert (!true_regnum (operands[1]));
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operands[4] = operands[1];
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operands[4] = operands[1];
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}
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}
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})
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}
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[(set_attr "type" "multi")
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(set_attr "mode" "<MODE>")])
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(define_insn "*divmod<mode>4_noext"
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(define_expand "divmodsi4"
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[(set (match_operand:SWI248 0 "register_operand" "=a")
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(div:SWI248 (match_operand:SWI248 2 "register_operand" "0")
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(div:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SWI248 3 "nonimmediate_operand" "rm")))
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(match_operand:SI 2 "nonimmediate_operand" "")))
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(set (match_operand:SWI248 1 "register_operand" "=d")
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(set (match_operand:SI 3 "register_operand" "")
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(mod:SWI248 (match_dup 2) (match_dup 3)))
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(mod:SI (match_dup 1) (match_dup 2)))
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(use (match_operand:SWI248 4 "register_operand" "1"))
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(clobber (reg:CC FLAGS_REG))])]
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(clobber (reg:CC FLAGS_REG))]
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""
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""
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"idiv{<imodesuffix>}\t%3"
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[(set_attr "type" "idiv")
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(set_attr "mode" "<MODE>")])
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(define_expand "udivmod<mode>4"
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[(parallel [(set (match_operand:SWI248 0 "register_operand" "")
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(udiv:SWI248
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(match_operand:SWI248 1 "register_operand" "")
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(match_operand:SWI248 2 "nonimmediate_operand" "")))
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(set (match_operand:SWI248 3 "register_operand" "")
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(umod:SWI248 (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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"(<MODE>mode != HImode) || TARGET_HIMODE_MATH"
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"")
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"")
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;; Allow to come the parameter in eax or edx to avoid extra moves.
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(define_insn_and_split "*udivmod<mode>4"
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;; Penalize eax case slightly because it results in worse scheduling
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[(set (match_operand:SWI248 0 "register_operand" "=a")
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;; of code.
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(udiv:SWI248 (match_operand:SWI248 2 "register_operand" "0")
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(define_insn "*divmodsi4_nocltd"
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(match_operand:SWI248 3 "nonimmediate_operand" "rm")))
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[(set (match_operand:SI 0 "register_operand" "=&a,?a")
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(set (match_operand:SWI248 1 "register_operand" "=&d")
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(div:SI (match_operand:SI 2 "register_operand" "1,0")
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(umod:SWI248 (match_dup 2) (match_dup 3)))
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(match_operand:SI 3 "nonimmediate_operand" "rm,rm")))
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(set (match_operand:SI 1 "register_operand" "=&d,&d")
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(mod:SI (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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(clobber (reg:CC FLAGS_REG))]
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"optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
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"(<MODE>mode != HImode) || TARGET_HIMODE_MATH"
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"#"
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"#"
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[(set_attr "type" "multi")])
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"&& reload_completed"
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[(set (match_dup 1) (const_int 0))
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(define_insn "*divmodsi4_cltd"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(div:SI (match_operand:SI 2 "register_operand" "a")
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(match_operand:SI 3 "nonimmediate_operand" "rm")))
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(set (match_operand:SI 1 "register_operand" "=&d")
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(mod:SI (match_dup 2) (match_dup 3)))
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(clobber (reg:CC FLAGS_REG))]
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"optimize_function_for_size_p (cfun) || TARGET_USE_CLTD"
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"#"
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[(set_attr "type" "multi")])
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(define_insn "*divmodsi_noext"
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[(set (match_operand:SI 0 "register_operand" "=a")
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(div:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "nonimmediate_operand" "rm")))
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(set (match_operand:SI 3 "register_operand" "=d")
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(mod:SI (match_dup 1) (match_dup 2)))
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(use (match_operand:SI 4 "register_operand" "3"))
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(clobber (reg:CC FLAGS_REG))]
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""
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"idiv{l}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "SI")])
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(define_split
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[(set (match_operand:SI 0 "register_operand" "")
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(div:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "nonimmediate_operand" "")))
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(set (match_operand:SI 3 "register_operand" "")
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(mod:SI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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[(parallel [(set (match_dup 3)
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(ashiftrt:SI (match_dup 4) (const_int 31)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel [(set (match_dup 0)
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(parallel [(set (match_dup 0)
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(div:SI (reg:SI 0) (match_dup 2)))
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(udiv:SWI248 (match_dup 2) (match_dup 3)))
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(set (match_dup 3)
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(set (match_dup 1)
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(mod:SI (reg:SI 0) (match_dup 2)))
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(umod:SWI248 (match_dup 2) (match_dup 3)))
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(use (match_dup 3))
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(use (match_dup 1))
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(clobber (reg:CC FLAGS_REG))])]
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(clobber (reg:CC FLAGS_REG))])]
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{
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/* Avoid use of cltd in favor of a mov+shift. */
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if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
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{
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if (true_regnum (operands[1]))
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emit_move_insn (operands[0], operands[1]);
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else
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emit_move_insn (operands[3], operands[1]);
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operands[4] = operands[3];
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}
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else
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{
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gcc_assert (!true_regnum (operands[1]));
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operands[4] = operands[1];
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}
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})
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;; %%% Split me.
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(define_insn "divmodhi4"
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[(set (match_operand:HI 0 "register_operand" "=a")
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(div:HI (match_operand:HI 1 "register_operand" "0")
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(match_operand:HI 2 "nonimmediate_operand" "rm")))
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(set (match_operand:HI 3 "register_operand" "=&d")
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(mod:HI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_HIMODE_MATH"
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"cwtd\;idiv{w}\t%2"
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[(set_attr "type" "multi")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "SI")])
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(define_insn "udivmoddi4"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(udiv:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(set (match_operand:DI 3 "register_operand" "=&d")
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(umod:DI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"xor{q}\t%3, %3\;div{q}\t%2"
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[(set_attr "type" "multi")
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(set_attr "length_immediate" "0")
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(set_attr "mode" "DI")])
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(define_insn "*udivmoddi4_noext"
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[(set (match_operand:DI 0 "register_operand" "=a")
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(udiv:DI (match_operand:DI 1 "register_operand" "0")
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(match_operand:DI 2 "nonimmediate_operand" "rm")))
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(set (match_operand:DI 3 "register_operand" "=d")
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(umod:DI (match_dup 1) (match_dup 2)))
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(use (match_dup 3))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_64BIT"
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"div{q}\t%2"
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[(set_attr "type" "idiv")
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(set_attr "mode" "DI")])
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(define_split
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||||||
[(set (match_operand:DI 0 "register_operand" "")
|
|
||||||
(udiv:DI (match_operand:DI 1 "register_operand" "")
|
|
||||||
(match_operand:DI 2 "nonimmediate_operand" "")))
|
|
||||||
(set (match_operand:DI 3 "register_operand" "")
|
|
||||||
(umod:DI (match_dup 1) (match_dup 2)))
|
|
||||||
(clobber (reg:CC FLAGS_REG))]
|
|
||||||
"TARGET_64BIT && reload_completed"
|
|
||||||
[(set (match_dup 3) (const_int 0))
|
|
||||||
(parallel [(set (match_dup 0)
|
|
||||||
(udiv:DI (match_dup 1) (match_dup 2)))
|
|
||||||
(set (match_dup 3)
|
|
||||||
(umod:DI (match_dup 1) (match_dup 2)))
|
|
||||||
(use (match_dup 3))
|
|
||||||
(clobber (reg:CC FLAGS_REG))])]
|
|
||||||
"")
|
|
||||||
|
|
||||||
(define_insn "udivmodsi4"
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
|
||||||
(udiv:SI (match_operand:SI 1 "register_operand" "0")
|
|
||||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
|
||||||
(set (match_operand:SI 3 "register_operand" "=&d")
|
|
||||||
(umod:SI (match_dup 1) (match_dup 2)))
|
|
||||||
(clobber (reg:CC FLAGS_REG))]
|
|
||||||
""
|
""
|
||||||
"xor{l}\t%3, %3\;div{l}\t%2"
|
|
||||||
[(set_attr "type" "multi")
|
[(set_attr "type" "multi")
|
||||||
(set_attr "length_immediate" "0")
|
(set_attr "mode" "<MODE>")])
|
||||||
(set_attr "mode" "SI")])
|
|
||||||
|
|
||||||
(define_insn "*udivmodsi4_noext"
|
(define_insn "*udivmod<mode>4_noext"
|
||||||
[(set (match_operand:SI 0 "register_operand" "=a")
|
[(set (match_operand:SWI248 0 "register_operand" "=a")
|
||||||
(udiv:SI (match_operand:SI 1 "register_operand" "0")
|
(udiv:SWI248 (match_operand:SWI248 2 "register_operand" "0")
|
||||||
(match_operand:SI 2 "nonimmediate_operand" "rm")))
|
(match_operand:SWI248 3 "nonimmediate_operand" "rm")))
|
||||||
(set (match_operand:SI 3 "register_operand" "=d")
|
(set (match_operand:SWI248 1 "register_operand" "=d")
|
||||||
(umod:SI (match_dup 1) (match_dup 2)))
|
(umod:SWI248 (match_dup 2) (match_dup 3)))
|
||||||
(use (match_dup 3))
|
(use (match_operand:SWI248 4 "register_operand" "1"))
|
||||||
(clobber (reg:CC FLAGS_REG))]
|
(clobber (reg:CC FLAGS_REG))]
|
||||||
""
|
"(<MODE>mode != HImode) || TARGET_HIMODE_MATH"
|
||||||
"div{l}\t%2"
|
"div{<imodesuffix>}\t%3"
|
||||||
[(set_attr "type" "idiv")
|
[(set_attr "type" "idiv")
|
||||||
(set_attr "mode" "SI")])
|
(set_attr "mode" "<MODE>")])
|
||||||
|
|
||||||
(define_split
|
|
||||||
[(set (match_operand:SI 0 "register_operand" "")
|
|
||||||
(udiv:SI (match_operand:SI 1 "register_operand" "")
|
|
||||||
(match_operand:SI 2 "nonimmediate_operand" "")))
|
|
||||||
(set (match_operand:SI 3 "register_operand" "")
|
|
||||||
(umod:SI (match_dup 1) (match_dup 2)))
|
|
||||||
(clobber (reg:CC FLAGS_REG))]
|
|
||||||
"reload_completed"
|
|
||||||
[(set (match_dup 3) (const_int 0))
|
|
||||||
(parallel [(set (match_dup 0)
|
|
||||||
(udiv:SI (match_dup 1) (match_dup 2)))
|
|
||||||
(set (match_dup 3)
|
|
||||||
(umod:SI (match_dup 1) (match_dup 2)))
|
|
||||||
(use (match_dup 3))
|
|
||||||
(clobber (reg:CC FLAGS_REG))])]
|
|
||||||
"")
|
|
||||||
|
|
||||||
(define_expand "udivmodhi4"
|
|
||||||
[(set (match_dup 4) (const_int 0))
|
|
||||||
(parallel [(set (match_operand:HI 0 "register_operand" "")
|
|
||||||
(udiv:HI (match_operand:HI 1 "register_operand" "")
|
|
||||||
(match_operand:HI 2 "nonimmediate_operand" "")))
|
|
||||||
(set (match_operand:HI 3 "register_operand" "")
|
|
||||||
(umod:HI (match_dup 1) (match_dup 2)))
|
|
||||||
(use (match_dup 4))
|
|
||||||
(clobber (reg:CC FLAGS_REG))])]
|
|
||||||
"TARGET_HIMODE_MATH"
|
|
||||||
"operands[4] = gen_reg_rtx (HImode);")
|
|
||||||
|
|
||||||
(define_insn "*udivmodhi_noext"
|
|
||||||
[(set (match_operand:HI 0 "register_operand" "=a")
|
|
||||||
(udiv:HI (match_operand:HI 1 "register_operand" "0")
|
|
||||||
(match_operand:HI 2 "nonimmediate_operand" "rm")))
|
|
||||||
(set (match_operand:HI 3 "register_operand" "=d")
|
|
||||||
(umod:HI (match_dup 1) (match_dup 2)))
|
|
||||||
(use (match_operand:HI 4 "register_operand" "3"))
|
|
||||||
(clobber (reg:CC FLAGS_REG))]
|
|
||||||
""
|
|
||||||
"div{w}\t%2"
|
|
||||||
[(set_attr "type" "idiv")
|
|
||||||
(set_attr "mode" "HI")])
|
|
||||||
|
|
||||||
;; We cannot use div/idiv for double division, because it causes
|
;; We cannot use div/idiv for double division, because it causes
|
||||||
;; "division by zero" on the overflow and that's not what we expect
|
;; "division by zero" on the overflow and that's not what we expect
|
||||||
|
|||||||
@ -871,8 +871,7 @@
|
|||||||
* gcc.dg/dfp/compare-special.h: Ditto.
|
* gcc.dg/dfp/compare-special.h: Ditto.
|
||||||
* gcc.dg/dfp/convert.h: Ditto.
|
* gcc.dg/dfp/convert.h: Ditto.
|
||||||
* gcc.dg/dfp/fe-check.h: Ditto.
|
* gcc.dg/dfp/fe-check.h: Ditto.
|
||||||
* gcc.dg/dfp/call-by-value.c: Use default options and
|
* gcc.dg/dfp/call-by-value.c: Use default options and debug macros.
|
||||||
debug macros.
|
|
||||||
* gcc.dg/dfp/cast.c: Ditto.
|
* gcc.dg/dfp/cast.c: Ditto.
|
||||||
* gcc.dg/dfp/compare-eq-const.c: Ditto.
|
* gcc.dg/dfp/compare-eq-const.c: Ditto.
|
||||||
* gcc.dg/dfp/compare-eq-d32.c: Ditto.
|
* gcc.dg/dfp/compare-eq-d32.c: Ditto.
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user