Fix the shift patterns, and add test
Firstly, it adds back the split conditions that I accidentally removed. Without it the dot insns are never generated, or rather, always split back to a separate compare instruction. Secondly, the shift amount should be SI always, not GPR, or GCC will insert a zero-extend at expand time that it cannot get rid of later. The test tests whether dot-form instructions are generated for both "dot" and "dot2" cases, that is, with just a CC output or also a GPR output; for all four basic shifts, with a register amount or an immediate amount. It also tests for superfluous zero-extends. This also tests if combine "simplifies" the rotates to right-rotates, which it shouldn't do anymore. From-SVN: r212267
This commit is contained in:
Segher Boessenkool
Segher Boessenkool
parent
07b6c04483
commit
9e5f78f114
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@ -1,3 +1,11 @@
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2014-07-03 Segher Boessenkool <segher@kernel.crashing.org>
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* config/rs6000/rs6000.md (rotl<mode>3, ashl<mode>3, lshr<mode>3,
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ashr<mode>3): Correct mode of operands[2].
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(rotl<mode>3_dot, rotl<mode>3_dot2, ashl<mode>3_dot, ashl<mode>3_dot2,
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lshr<mode>3_dot, lshr<mode>3_dot2, ashr<mode>3_dot, ashr<mode>3_dot2):
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Correct mode of operands[2]. Fix split condition.
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2014-07-03 Richard Earnshaw <rearnsha@arm.com>
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* arm.md (arch): Add armv6_or_vfpv3.
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@ -3874,7 +3874,7 @@
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(define_insn "rotl<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn")))]
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(match_operand:SI 2 "reg_or_cint_operand" "rn")))]
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""
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"rotl<wd>%I2 %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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@ -3893,14 +3893,14 @@
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(define_insn_and_split "*rotl<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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rotl<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(rotate:GPR (match_dup 1)
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(match_dup 2)))
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@ -3916,7 +3916,7 @@
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(define_insn_and_split "*rotl<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (rotate:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(rotate:GPR (match_dup 1)
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@ -3925,7 +3925,7 @@
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"@
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rotl<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(rotate:GPR (match_dup 1)
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(match_dup 2)))
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@ -4353,7 +4353,7 @@
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(define_insn "ashl<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn")))]
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(match_operand:SI 2 "reg_or_cint_operand" "rn")))]
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""
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"sl<wd>%I2 %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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@ -4372,14 +4372,14 @@
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(define_insn_and_split "*ashl<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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sl<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(ashift:GPR (match_dup 1)
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(match_dup 2)))
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@ -4395,7 +4395,7 @@
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(define_insn_and_split "*ashl<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(ashift:GPR (match_dup 1)
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@ -4404,7 +4404,7 @@
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"@
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sl<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(ashift:GPR (match_dup 1)
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(match_dup 2)))
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@ -4498,7 +4498,7 @@
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(define_insn "lshr<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn")))]
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(match_operand:SI 2 "reg_or_cint_operand" "rn")))]
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""
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"sr<wd>%I2 %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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@ -4517,14 +4517,14 @@
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(define_insn_and_split "*lshr<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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sr<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(lshiftrt:GPR (match_dup 1)
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(match_dup 2)))
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@ -4540,7 +4540,7 @@
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(define_insn_and_split "*lshr<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(lshiftrt:GPR (match_dup 1)
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@ -4549,7 +4549,7 @@
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"@
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sr<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(lshiftrt:GPR (match_dup 1)
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(match_dup 2)))
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@ -4971,7 +4971,7 @@
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(define_expand "ashr<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "")
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(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
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(match_operand:GPR 2 "reg_or_cint_operand" "")))]
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(match_operand:SI 2 "reg_or_cint_operand" "")))]
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""
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{
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/* The generic code does not generate optimal code for the low word
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@ -4993,7 +4993,7 @@
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(define_insn "*ashr<mode>3"
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[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
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(ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn")))]
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(match_operand:SI 2 "reg_or_cint_operand" "rn")))]
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""
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"sra<wd>%I2 %0,%1,%<hH>2"
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[(set_attr "type" "shift")
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@ -5012,14 +5012,14 @@
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(define_insn_and_split "*ashr<mode>3_dot"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(clobber (match_scratch:GPR 0 "=r,r"))]
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"<MODE>mode == Pmode && rs6000_gen_cell_microcode"
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"@
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sra<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(ashiftrt:GPR (match_dup 1)
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(match_dup 2)))
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@ -5035,7 +5035,7 @@
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(define_insn_and_split "*ashr<mode>3_dot2"
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[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
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(compare:CC (ashiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r")
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(match_operand:GPR 2 "reg_or_cint_operand" "rn,rn"))
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(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
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(const_int 0)))
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(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
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(ashiftrt:GPR (match_dup 1)
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@ -5044,7 +5044,7 @@
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"@
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sra<wd>%I2. %0,%1,%<hH>2
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#"
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"&& reload_completed"
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"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
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[(set (match_dup 0)
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(ashiftrt:GPR (match_dup 1)
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(match_dup 2)))
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@ -1,3 +1,7 @@
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2014-07-03 Segher Boessenkool <segher@kernel.crashing.org>
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* gcc.target/powerpc/shift-dot.c: New test.
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2014-07-03 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
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* gfortran.dg/ieee/ieee_1.F90: Mark variables as volatile to
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@ -0,0 +1,49 @@
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/* Check that record-form instructions are used. */
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/* { dg-do compile } */
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/* { dg-options "-O2 -mgen-cell-microcode" } */
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/* { dg-final { scan-assembler-times {\mrotl[wd]\.} 2 } } */
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/* { dg-final { scan-assembler-times {\msl[wd]\.} 2 } } */
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/* { dg-final { scan-assembler-times {\msr[wd]\.} 2 } } */
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/* { dg-final { scan-assembler-times {\msra[wd]\.} 2 } } */
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/* { dg-final { scan-assembler-times {\mrotl[wd]i\.} 2 } } */
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/* { dg-final { scan-assembler-times {\msl[wd]i\.} 2 } } */
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/* { dg-final { scan-assembler-times {\msr[wd]i\.} 2 } } */
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/* Combine converts the arith shift right compares to a (more expensive)
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direct compare. Luckily not the other shifts. XFAIL for now. */
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/* { dg-final { scan-assembler-times {\msra[wd]i\.} 2 { xfail *-*-* } } } */
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/* There should not be any extends of the shift amount (or anything else). */
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/* { dg-final { scan-assembler-not {\mextsw\M} } } */
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/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
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/* { dg-final { scan-assembler-not {\mclrldi\M} } } */
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/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
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typedef unsigned long u;
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typedef long s;
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#define M(n) (8 * sizeof(long) - (n))
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#define T1 if ((s)x > 0) g();
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#define T2 if ((s)x > 0) g(); return x;
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void g(void);
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void rot1(u x, u n) { x = (x << M(n)) | (x >> n); T1 }
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u rot2(u x, u n) { x = (x << M(n)) | (x >> n); T2 }
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void shl1(u x, u n) { x <<= n; T1 }
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u shl2(u x, u n) { x <<= n; T2 }
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void shr1(u x, u n) { x >>= n; T1 }
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u shr2(u x, u n) { x >>= n; T2 }
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void asr1(s x, u n) { x >>= n; T1 }
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s asr2(s x, u n) { x >>= n; T2 }
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void rot1i(u x) { x = (x << M(23)) | (x >> 23); T1 }
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u rot2i(u x) { x = (x << M(23)) | (x >> 23); T2 }
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void shl1i(u x) { x <<= 23; T1 }
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u shl2i(u x) { x <<= 23; T2 }
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void shr1i(u x) { x >>= 23; T1 }
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u shr2i(u x) { x >>= 23; T2 }
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void asr1i(s x) { x >>= 23; T1 }
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s asr2i(s x) { x >>= 23; T2 }
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