[ARC] Deprecate q-class option.
This option was used to control the short instruction selection. However, there is no difference in cycles if we use or not a short instruction, and always someone wants a smaller program. gcc/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_conditional_register_usage): R0-R3 and R12-R15 are always in ARCOMPACT16_REGS register class. * config/arc/arc.opt (mq-class): Deprecate. * config/arc/constraint.md ("q"): Remove dependency on mq-class option. * doc/invoke.texi (mq-class): Update text. * common/config/arc/arc-common.c (arc_option_optimization_table): Update list. testsuite/ xxxx-xx-xx Claudiu Zissulescu <claziss@synopsys.com> * gcc.target/arc/nps400-1.c: Update test.
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@ -1,3 +1,14 @@
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2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (arc_conditional_register_usage): R0-R3 and
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R12-R15 are always in ARCOMPACT16_REGS register class.
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* config/arc/arc.opt (mq-class): Deprecate.
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* config/arc/constraint.md ("q"): Remove dependency on mq-class
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option.
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* doc/invoke.texi (mq-class): Update text.
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* common/config/arc/arc-common.c (arc_option_optimization_table):
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Update list.
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2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
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* config/arc/arc.c (arc_insn_cost): New function.
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@ -56,7 +56,6 @@ static const struct default_options arc_option_optimization_table[] =
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{ OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0},
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{ OPT_LEVELS_SIZE, OPT_fdelayed_branch, NULL, 0 },
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{ OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
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{ OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
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{ OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
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{ OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
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{ OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 },
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@ -1427,9 +1427,6 @@ arc_override_options (void)
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if (flag_no_common == 255)
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flag_no_common = !TARGET_NO_SDATA_SET;
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if (TARGET_MIXED_CODE)
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TARGET_Q_CLASS = 1;
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/* Check for small data option */
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if (!global_options_set.x_g_switch_value && !TARGET_NO_SDATA_SET)
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g_switch_value = TARGET_LL64 ? 8 : 4;
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@ -1956,8 +1953,7 @@ arc_conditional_register_usage (void)
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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if (i < ILINK1_REG)
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{
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if ((TARGET_Q_CLASS || TARGET_RRQ_CLASS)
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&& ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG))))
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if ((i <= R3_REG) || ((i >= R12_REG) && (i <= R15_REG)))
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arc_regno_reg_class[i] = ARCOMPACT16_REGS;
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else
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arc_regno_reg_class[i] = GENERAL_REGS;
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@ -335,7 +335,7 @@ Target Warn(%qs is deprecated)
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Enable compact casesi pattern.
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mq-class
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Target Var(TARGET_Q_CLASS)
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Target Warn(%qs is deprecated)
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Enable 'q' instruction alternatives.
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mexpand-adddi
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@ -53,7 +53,7 @@
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(define_register_constraint "x" "R0_REGS"
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"@code{R0} register.")
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(define_register_constraint "q" "TARGET_Q_CLASS ? ARCOMPACT16_REGS : NO_REGS"
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(define_register_constraint "q" "ARCOMPACT16_REGS"
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"Registers usable in ARCompact 16-bit instructions: @code{r0}-@code{r3},
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@code{r12}-@code{r15}")
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@ -17845,7 +17845,7 @@ while increasing the instruction count.
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@item -mq-class
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@opindex mq-class
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Enable @samp{q} instruction alternatives.
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Ths option is deprecated. Enable @samp{q} instruction alternatives.
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This is the default for @option{-Os}.
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@item -mRcq
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@ -1,3 +1,7 @@
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2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
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* gcc.target/arc/nps400-1.c: Update test.
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2020-02-13 Claudiu Zissulescu <claziss@synopsys.com>
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* gcc.target/arc/or-cnst-size2.c: Update test.
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-skip-if "" { ! { clmcpu } } } */
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/* { dg-options "-mcpu=nps400 -mq-class -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
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/* { dg-options "-mcpu=nps400 -mbitops -munaligned-access -mcmem -O2 -fno-strict-aliasing" } */
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enum npsdp_mem_space_type {
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NPSDP_EXTERNAL_MS = 1
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