mn10300: Explicitly represent MDR in multiply and divide.
Note that the mulsidi3_internal pattern is structured so as to let the lower-subregs pass fully split the result. From-SVN: r169008
This commit is contained in:
Richard Henderson
Richard Henderson
parent
c25a21f581
commit
9efb4993cb
@ -1,5 +1,20 @@
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2011-01-19 Richard Henderson <rth@redhat.com>
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* config/mn10300/mn10300.md (UNSPEC_EXT): New.
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(throughput_42_latency_43): New reservation.
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(mulsidi3, umulsidi3): New expanders.
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(mulsidi3_internal): Rewrite from old mulsidi3 pattern. Expose
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the MDR register to allocation; separately allocate the low and
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high parts of the DImode result.
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(umulsidi3_internal): Similarly.
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(*am33_mulsi3, *mn10300_mulsi3): Merge into ...
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(*mulsi3): ... here. Clobber MDR as a scratch as necessary.
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(udivsi3, umodsi3): Remove.
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(udivmodsi4, divmodsi4): New expanders.
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(*udivmodsi4): Rename from udivmodsi4. Expose MDR properly.
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(*divmodsi4): Simiarly.
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(ext_internal): New.
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* config/mn10300/constraints.md ("z"): New constraint.
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* config/mn10300/mn10300.h (MDR_REGNUM): Remove.
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(FIXED_REGISTERS): Don't fix MDR.
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@ -38,6 +38,7 @@
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(UNSPEC_PLT 4)
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(UNSPEC_GOTSYM_OFF 5)
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(UNSPEC_EXT 6)
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(UNSPEC_BSCH 7)
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])
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@ -167,6 +168,8 @@
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(eq_attr "timings" "4040") "throughput*40")
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(define_insn_reservation "throughput_41_latency_42" 42
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(eq_attr "timings" "4142") "throughput*41,nothing")
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(define_insn_reservation "throughput_42_latency_43" 44
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(eq_attr "timings" "4243") "throughput*42,nothing")
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(define_insn_reservation "throughput_43_latency_44" 44
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(eq_attr "timings" "4344") "throughput*43,nothing")
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(define_insn_reservation "throughput_45_latency_46" 46
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@ -748,148 +751,183 @@
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;; MULTIPLY INSTRUCTIONS
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;; ----------------------------------------------------------------------
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(define_insn "mulsidi3"
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[(set (match_operand:DI 0 "register_operand" "=dax")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "dax"))
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(sign_extend:DI (match_operand:SI 2 "register_operand" "dax"))))
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(clobber (reg:CC CC_REG))
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]
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"TARGET_AM33"
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"mul %1,%2,%H0,%L0"
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 24) (const_int 23)))]
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;; ??? Note that AM33 has a third multiply variant that puts the high part
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;; into the MDRQ register, however this variant also constrains the inputs
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;; to be in DATA_REGS and thus isn't as helpful as it might be considering
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;; the existance of the 4-operand multiply. Nor is there a set of divide
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;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would
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;; have been very handy for starting udivmodsi4...
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(define_expand "mulsidi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
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(sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
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""
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{
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emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]),
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gen_highpart (SImode, operands[0]),
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operands[1], operands[2]));
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DONE;
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})
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(define_insn "mulsidi3_internal"
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[(set (match_operand:SI 0 "register_operand" "=D,r")
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(mult:SI (match_operand:SI 2 "register_operand" "%0,r")
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(match_operand:SI 3 "register_operand" " D,r")))
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(set (match_operand:SI 1 "register_operand" "=z,r")
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(truncate:SI
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(ashiftrt:DI
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(mult:DI (sign_extend:DI (match_dup 2))
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(sign_extend:DI (match_dup 3)))
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(const_int 32))))
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(clobber (reg:CC CC_REG))]
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""
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{
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if (which_alternative == 1)
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return "mul %2,%3,%1,%0";
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else if (TARGET_MULT_BUG)
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return "nop\;nop\;mul %3,%0";
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else
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return "mul %3,%0";
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}
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[(set_attr "isa" "*,am33")
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(set (attr "timings")
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(if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
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)
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(define_insn "umulsidi3"
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[(set (match_operand:DI 0 "register_operand" "=dax")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "dax"))
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(zero_extend:DI (match_operand:SI 2 "register_operand" "dax"))))
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(clobber (reg:CC CC_REG))
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]
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"TARGET_AM33"
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"mulu %1,%2,%H0,%L0"
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 24) (const_int 23)))]
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(define_expand "umulsidi3"
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[(set (match_operand:DI 0 "register_operand" "")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
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(zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
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(clobber (reg:CC CC_REG))]
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""
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{
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emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]),
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gen_highpart (SImode, operands[0]),
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operands[1], operands[2]));
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DONE;
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})
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(define_insn "umulsidi3_internal"
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[(set (match_operand:SI 0 "register_operand" "=D,r")
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(mult:SI (match_operand:SI 2 "register_operand" "%0,r")
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(match_operand:SI 3 "register_operand" " D,r")))
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(set (match_operand:SI 1 "register_operand" "=z,r")
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(truncate:SI
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(lshiftrt:DI
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(mult:DI (zero_extend:DI (match_dup 2))
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(zero_extend:DI (match_dup 3)))
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(const_int 32))))
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(clobber (reg:CC CC_REG))]
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""
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{
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if (which_alternative == 1)
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return "mulu %2,%3,%1,%0";
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else if (TARGET_MULT_BUG)
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return "nop\;nop\;mulu %3,%0";
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else
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return "mulu %3,%0";
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}
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[(set_attr "isa" "*,am33")
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(set (attr "timings")
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(if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
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)
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(define_expand "mulsi3"
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[(parallel [(set (match_operand:SI 0 "register_operand")
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(mult:SI (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "register_operand")))
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(clobber (reg:CC CC_REG))
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])
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]
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(mult:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "nonmemory_operand" "")))
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(clobber (match_scratch:SI 3 ""))
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(clobber (reg:CC CC_REG))])]
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""
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"")
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(define_insn "*am33_mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=dx,!dax")
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(mult:SI (match_operand:SI 1 "register_operand" "%0,0")
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(match_operand:SI 2 "nonmemory_operand" "dx,daxi")))
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(clobber (reg:CC CC_REG))
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]
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"TARGET_AM33"
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"*
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{
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if (TARGET_MULT_BUG)
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return \"nop\;nop\;mul %2,%0\";
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else
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return \"mul %2,%0\";
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}"
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
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)
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(define_insn "*mn10300_mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=dx")
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(mult:SI (match_operand:SI 1 "register_operand" "%0")
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(match_operand:SI 2 "register_operand" "dx")))
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(clobber (reg:CC CC_REG))
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]
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""
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"*
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{
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if (TARGET_MULT_BUG)
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return \"nop\;nop\;mul %2,%0\";
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else
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return \"mul %2,%0\";
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}"
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 24) (const_int 23)))]
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)
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;; ??? This pattern causes too-high register pressure for MN103.
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;; ??? To be fixed by exposing the MDR register properly.
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(define_insn "udivmodsi4"
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[(set (match_operand:SI 0 "register_operand" "=D")
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(udiv:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "D")))
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(set (match_operand:SI 3 "register_operand" "=&d")
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(umod:SI (match_dup 1) (match_dup 2)))
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(define_insn "*mulsi3"
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[(set (match_operand:SI 0 "register_operand" "=D, r,r")
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(mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r")
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(match_operand:SI 3 "nonmemory_operand" " D,ri,r")))
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(clobber (match_scratch:SI 1 "=z, z,r"))
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(clobber (reg:CC CC_REG))]
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"TARGET_AM33"
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""
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{
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output_asm_insn ("clr %3\;ext %3", operands);
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if (find_reg_note (insn, REG_UNUSED, operands[3]))
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return "divu %2,%0";
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if (which_alternative == 2)
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return "mul %2,%3,%1,%0";
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else if (TARGET_MULT_BUG)
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return "nop\;nop\;mul %3,%0";
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else
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return "divu %2,%0\;mov mdr,%3";
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return "mul %3,%0";
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}
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;; Timings: AM33 AM34
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;; SUB 1/1 1/1
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;; MOV 1/1 1/1
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;; DIVU 38/39 42/43
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;; MOV 1/1 1/1
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;; --------------------
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;; total 41/42 45/46 (worst case sceanario)
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 4546) (const_int 4142)))]
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[(set_attr "isa" "*,am33,am33")
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(set (attr "timings")
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(if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
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)
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;; ??? In the meantime MN103 can use these two patterns,
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;; which reduce the register pressure by one.
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(define_insn "udivsi3"
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[(set (match_operand:SI 0 "register_operand" "=&d")
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(udiv:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))
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(clobber (reg:CC CC_REG))]
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"!TARGET_AM33"
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"clr %0\;ext %0\;mov %1,%0\;divu %2,%0"
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[(set_attr "timings" "4142")]
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)
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(define_insn "umodsi3"
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[(set (match_operand:SI 0 "register_operand" "=&d")
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(umod:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))
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(clobber (reg:CC CC_REG))]
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"!TARGET_AM33"
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"clr %0\;ext %0\;mov %1,%0\;divu %2,%0\;mov mdr,%0"
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[(set_attr "timings" "4142")]
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)
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(define_insn "divmodsi4"
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[(set (match_operand:SI 0 "register_operand" "=dx")
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(div:SI (match_operand:SI 1 "register_operand" "0")
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(match_operand:SI 2 "register_operand" "dx")))
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(set (match_operand:SI 3 "register_operand" "=d")
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(mod:SI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC CC_REG))
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]
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(define_expand "udivmodsi4"
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[(parallel [(set (match_operand:SI 0 "register_operand")
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(udiv:SI (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "register_operand")))
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(set (match_operand:SI 3 "register_operand")
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(umod:SI (match_dup 1) (match_dup 2)))
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(use (const_int 0))
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(clobber (reg:CC CC_REG))])]
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""
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"*
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{
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if (find_reg_note (insn, REG_UNUSED, operands[3]))
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return \"ext %0\;div %2,%0\";
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else
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return \"ext %0\;div %2,%0\;mov mdr,%3\";
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}"
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;; Timings: AM33 AM34
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;; EXT 1/1 1/1
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;; DIV 38/39 42/43
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;; --------------------
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;; total 39/40 43/44 (worst case sceanario)
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)
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;; Note the trick to get reload to put the zero into the MDR register,
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;; rather than exposing the load early and letting CSE or someone try
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;; to share the zeros between division insns. Which tends to result
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;; in sequences like 0->r0->d0->mdr.
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(define_insn "*udivmodsi4"
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[(set (match_operand:SI 0 "register_operand" "=D")
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(udiv:SI (match_operand:SI 2 "register_operand" " 0")
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(match_operand:SI 3 "register_operand" " D")))
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(set (match_operand:SI 1 "register_operand" "=z")
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(umod:SI (match_dup 2) (match_dup 3)))
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(use (match_operand:SI 4 "nonmemory_operand" " 1"))
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(clobber (reg:CC CC_REG))]
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""
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"divu %3,%0"
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 4344) (const_int 3940)))]
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(const_int 3839) (const_int 4243)))]
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)
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(define_expand "divmodsi4"
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[(parallel [(set (match_operand:SI 0 "register_operand" "")
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(div:SI (match_operand:SI 1 "register_operand" "")
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(match_operand:SI 2 "register_operand" "")))
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(set (match_operand:SI 3 "register_operand" "")
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(mod:SI (match_dup 1) (match_dup 2)))
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(use (match_dup 4))
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(clobber (reg:CC CC_REG))])]
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""
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{
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operands[4] = gen_reg_rtx (SImode);
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emit_insn (gen_ext_internal (operands[4], operands[1]));
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})
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;; ??? Ideally we'd represent this via shift, but it seems like adding a
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;; special-case pattern for (ashiftrt x 31) is just as likely to result
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;; in poor register allocation choices.
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(define_insn "ext_internal"
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[(set (match_operand:SI 0 "register_operand" "=z")
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(unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))]
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""
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"ext %1"
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)
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(define_insn "*divmodsi4"
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[(set (match_operand:SI 0 "register_operand" "=D")
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(div:SI (match_operand:SI 2 "register_operand" " 0")
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(match_operand:SI 3 "register_operand" " D")))
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(set (match_operand:SI 1 "register_operand" "=z")
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(mod:SI (match_dup 2) (match_dup 3)))
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(use (match_operand:SI 4 "register_operand" " 1"))
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(clobber (reg:CC CC_REG))]
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""
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"div %3,%0";
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[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
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(const_int 3839) (const_int 4243)))]
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)
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