config.gcc: Added support for --with-divide=[breaks|traps] for mips targets.
2004-09-07 David Daney <ddaney@avtrex.com> * config.gcc: Added support for --with-divide=[breaks|traps] for mips targets. * config/mips/mips.h (MASK_DIVIDE_BREAKS): New target_flags bit. (TARGET_DIVIDE_TRAPS): New macro. (TARGET_SWITCHES): Added -mdivide-traps and -mdivide-breaks. (OPTION_DEFAULT_SPECS): Added --with-divide= support. * config/mips/mips.c (mips_idiv_insns): Generate proper count on GENERATE_DIVIDE_TRAPS. (mips_output_division): Emit conditional trap if GENERATE_DIVIDE_TRAPS is set. * doc/install.texi: Document --with-divide. * doc/invoke.texi: Document -mdivide-traps and -mdivide-breaks. From-SVN: r87153
This commit is contained in:
David Daney
David Daney
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9f0df97afb
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@ -1,3 +1,18 @@
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2004-09-07 David Daney <ddaney@avtrex.com>
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* config.gcc: Added support for --with-divide=[breaks|traps] for
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mips targets.
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* config/mips/mips.h (MASK_DIVIDE_BREAKS): New target_flags bit.
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(TARGET_DIVIDE_TRAPS): New macro.
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(TARGET_SWITCHES): Added -mdivide-traps and -mdivide-breaks.
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(OPTION_DEFAULT_SPECS): Added --with-divide= support.
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* config/mips/mips.c (mips_idiv_insns): Generate proper count on
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GENERATE_DIVIDE_TRAPS.
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(mips_output_division): Emit conditional trap if
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GENERATE_DIVIDE_TRAPS is set.
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* doc/install.texi: Document --with-divide.
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* doc/invoke.texi: Document -mdivide-traps and -mdivide-breaks.
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2004-09-07 Caroline Tice <ctice@apple.com>
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* cfgrtl.c (rtl_verify_flow_info_1): Add new edge flag,
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@ -2425,7 +2425,7 @@ fi
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;;
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mips*-*-*)
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supported_defaults="abi arch float tune"
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supported_defaults="abi arch float tune divide"
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case ${with_float} in
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"" | soft | hard)
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@ -2446,6 +2446,15 @@ fi
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exit 1
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;;
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esac
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case ${with_divide} in
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"" | breaks | traps)
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# OK
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;;
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*)
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echo "Unknown division check type use in --with-divide=$with_divide" 1>&2
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exit 1
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esac
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;;
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powerpc*-*-* | rs6000-*-*)
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@ -2687,7 +2696,7 @@ fi
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esac
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t=
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all_defaults="abi cpu arch tune schedule float mode fpu"
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all_defaults="abi cpu arch tune schedule float mode fpu divide"
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for option in $all_defaults
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do
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eval "val=\$with_$option"
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@ -1375,7 +1375,13 @@ mips_idiv_insns (void)
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count = 1;
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if (TARGET_CHECK_ZERO_DIV)
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count += 2;
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{
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if (GENERATE_DIVIDE_TRAPS)
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count++;
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else
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count += 2;
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}
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if (TARGET_FIX_R4000 || TARGET_FIX_R4400)
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count++;
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return count;
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@ -8805,6 +8811,11 @@ mips_output_division (const char *division, rtx *operands)
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output_asm_insn (s, operands);
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s = "bnez\t%2,1f\n\tbreak\t7\n1:";
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}
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else if (GENERATE_DIVIDE_TRAPS)
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{
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output_asm_insn (s, operands);
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s = "teq\t%2,%.,7";
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}
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else
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{
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output_asm_insn ("%(bne\t%2,%.,1f", operands);
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@ -160,7 +160,8 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
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#define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
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#define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
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#define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
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break instead of trap. */
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#define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
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#define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
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@ -222,6 +223,7 @@ extern const struct mips_cpu_info *mips_tune_info;
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#define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
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#define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
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#define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
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#define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
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@ -632,6 +634,10 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("Trap on integer divide by zero")}, \
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{"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
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N_("Don't trap on integer divide by zero")}, \
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{"divide-traps", -MASK_DIVIDE_BREAKS, \
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N_("Use trap to check for integer divide by zero")}, \
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{"divide-breaks", MASK_DIVIDE_BREAKS, \
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N_("Use break to check for integer divide by zero")}, \
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{ "branch-likely", MASK_BRANCHLIKELY, \
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N_("Use Branch Likely instructions, overriding default for arch")}, \
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{ "no-branch-likely", -MASK_BRANCHLIKELY, \
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@ -782,14 +788,20 @@ extern const struct mips_cpu_info *mips_tune_info;
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--with-tune is ignored if -mtune is specified.
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--with-abi is ignored if -mabi is specified.
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--with-float is ignored if -mhard-float or -msoft-float are
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specified. */
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specified.
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--with-divide is ignored if -mdivide-traps or -mdivide-breaks are
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specified. */
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#define OPTION_DEFAULT_SPECS \
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{"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
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{"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
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{"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
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{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
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{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
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{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
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#define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
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&& ISA_HAS_COND_TRAP)
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#define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
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&& !TARGET_SR71K \
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&& !TARGET_MIPS16)
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@ -959,6 +959,18 @@ options and for @option{-mhard-float} or @option{-msoft-float}. As with
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@option{--with-cpu}, which switches will be accepted and acceptable values
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of the arguments depend on the target.
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@item --with-divide=@var{type}
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Specify how the compiler should generate code for checking for
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division by zero. This option is only supported on the MIPS target.
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The possibilities for @var{type} are:
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@table @code
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@item traps
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Division by zero checks use conditional traps (this is the default on
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systems that support conditional traps).
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@item breaks
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Division by zero checks use the break instruction.
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@end table
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@item --enable-altivec
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Specify that the target supports AltiVec vector enhancements. This
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option will adjust the ABI for AltiVec enhancements, as well as generate
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@ -3201,6 +3213,16 @@ configure for @samp{mipsel-elf} as a workaround. The
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@samp{mips*-*-linux*} target continues to use the MIPS II routines. More
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work on this is expected in future releases.
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MIPS systems check for division by zero (unless
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@option{-mno-check-zero-division} is passed to the compiler) by
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generating either a conditional trap or a break instruction. Using
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trap results in smaller code, but is only supported on MIPS II and
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later. Also, some versions of the Linux kernel have a bug that
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prevents trap from generating the proper signal (SIGFPE). To enable
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the use of break, use the @option{--with-divide=breaks}
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@command{configure} option when configuring GCC. The default is to
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use traps on systems that support them.
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Cross-compilers for the Mips as target using the Mips assembler
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currently do not work, because the auxiliary programs
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@file{mips-tdump.c} and @file{mips-tfile.c} can't be compiled on
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@ -545,6 +545,7 @@ Objective-C and Objective-C++ Dialects}.
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-msplit-addresses -mno-split-addresses @gol
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-mexplicit-relocs -mno-explicit-relocs @gol
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-mcheck-zero-division -mno-check-zero-division @gol
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-mdivide-traps -mdivide-breaks @gol
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-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
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-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
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-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
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@ -9500,6 +9501,23 @@ to use an assembler that supports relocation operators.
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Trap (do not trap) on integer division by zero. The default is
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@option{-mcheck-zero-division}.
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@item -mdivide-traps
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@itemx -mdivide-breaks
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@opindex mdivide-traps
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@opindex mdivide-breaks
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MIPS systems check for division by zero by generating either a
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conditional trap or a break instruction. Using traps results in
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smaller code, but is only supported on MIPS II and later. Also, some
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versions of the Linux kernel have a bug that prevents trap from
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generating the proper signal (SIGFPE). Use @option{-mdivide-traps} to
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allow conditional traps on architectures that support them and
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@option{-mdivide-breaks} to force the use of breaks.
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The default is usually @option{-mdivide-traps}, but this can be
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overridden at configure time using @option{--with-divide=breaks}.
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Divide-by-zero checks can be completely disabled using
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@option{-mno-check-zero-division}.
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@item -mmemcpy
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@itemx -mno-memcpy
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@opindex mmemcpy
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