arm: Enable no-writeback vldr.16/vstr.16.
There was previously no way to specify that a register operand cannot have any writeback modifiers, and as a result the argument to vldr.16 and vstr.16 could be erroneously output with post-increment. This change adds a constraint which forbids all writeback, and selects it in the relevant case for vldr.16 and vstr.16 Bootstrapped on arm-linux, gcc and CMSIS-DSP testsuites are clean. Is this patch OK for trunk? If yes, please commit on my behalf as I don't have commit rights. gcc/ChangeLog: * config/arm/arm-protos.h (arm_coproc_mem_operand_no_writeback): Declare prototype. (arm_mve_mode_and_operands_type_check): Declare prototype. * config/arm/arm.c (arm_coproc_mem_operand): Refactor to use _arm_coproc_mem_operand. (arm_coproc_mem_operand_wb): New function to cover full, limited and no writeback. (arm_coproc_mem_operand_no_writeback): New constraint for memory operand with no writeback. (arm_print_operand): Extend 'E' specifier for memory operand that does not support writeback. (arm_mve_mode_and_operands_type_check): New constraint check for MVE memory operands. * config/arm/constraints.md: Add Uj constraint for VFP vldr.16 and vstr.16. * config/arm/vfp.md (*mov_load_vfp_hf16): New pattern for vldr.16. (*mov_store_vfp_hf16): New pattern for vstr.16. (*mov<mode>_vfp_<mode>16): Remove MVE moves.
This commit is contained in:
Joe Ramsay
Kyrylo Tkachov
parent
5175857714
commit
9f6abd2db9
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@ -116,8 +116,11 @@ extern enum reg_class coproc_secondary_reload_class (machine_mode, rtx,
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extern bool arm_tls_referenced_p (rtx);
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extern int arm_coproc_mem_operand (rtx, bool);
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extern int arm_coproc_mem_operand_no_writeback (rtx);
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extern int arm_coproc_mem_operand_wb (rtx, int);
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extern int neon_vector_mem_operand (rtx, int, bool);
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extern int mve_vector_mem_operand (machine_mode, rtx, bool);
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bool arm_mve_mode_and_operands_type_check (machine_mode, rtx, rtx);
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extern int neon_struct_mem_operand (rtx);
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extern rtx *neon_vcmla_lane_prepare_operands (rtx *);
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@ -13235,13 +13235,14 @@ neon_element_bits (machine_mode mode)
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/* Predicates for `match_operand' and `match_operator'. */
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/* Return TRUE if OP is a valid coprocessor memory address pattern.
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WB is true if full writeback address modes are allowed and is false
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WB level is 2 if full writeback address modes are allowed, 1
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if limited writeback address modes (POST_INC and PRE_DEC) are
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allowed. */
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allowed and 0 if no writeback at all is supported. */
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int
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arm_coproc_mem_operand (rtx op, bool wb)
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arm_coproc_mem_operand_wb (rtx op, int wb_level)
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{
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gcc_assert (wb_level == 0 || wb_level == 1 || wb_level == 2);
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rtx ind;
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/* Reject eliminable registers. */
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@ -13274,16 +13275,18 @@ arm_coproc_mem_operand (rtx op, bool wb)
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/* Autoincremment addressing modes. POST_INC and PRE_DEC are
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acceptable in any case (subject to verification by
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arm_address_register_rtx_p). We need WB to be true to accept
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arm_address_register_rtx_p). We need full writeback to accept
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PRE_INC and POST_DEC, and at least restricted writeback for
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PRE_INC and POST_DEC. */
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if (GET_CODE (ind) == POST_INC
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|| GET_CODE (ind) == PRE_DEC
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|| (wb
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&& (GET_CODE (ind) == PRE_INC
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|| GET_CODE (ind) == POST_DEC)))
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if (wb_level > 0
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&& (GET_CODE (ind) == POST_INC
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|| GET_CODE (ind) == PRE_DEC
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|| (wb_level > 1
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&& (GET_CODE (ind) == PRE_INC
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|| GET_CODE (ind) == POST_DEC))))
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return arm_address_register_rtx_p (XEXP (ind, 0), 0);
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if (wb
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if (wb_level > 1
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&& (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY)
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&& arm_address_register_rtx_p (XEXP (ind, 0), 0)
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&& GET_CODE (XEXP (ind, 1)) == PLUS
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@ -13305,6 +13308,25 @@ arm_coproc_mem_operand (rtx op, bool wb)
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return FALSE;
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}
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/* Return TRUE if OP is a valid coprocessor memory address pattern.
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WB is true if full writeback address modes are allowed and is false
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if limited writeback address modes (POST_INC and PRE_DEC) are
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allowed. */
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int arm_coproc_mem_operand (rtx op, bool wb)
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{
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return arm_coproc_mem_operand_wb (op, wb ? 2 : 1);
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}
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/* Return TRUE if OP is a valid coprocessor memory address pattern in a
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context in which no writeback address modes are allowed. */
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int
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arm_coproc_mem_operand_no_writeback (rtx op)
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{
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return arm_coproc_mem_operand_wb (op, 0);
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}
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/* This function returns TRUE on matching mode and op.
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1. For given modes, check for [Rn], return TRUE for Rn <= LO_REGS.
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2. For other modes, check for [Rn], return TRUE for Rn < R15 (expect R13). */
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@ -23568,7 +23590,7 @@ arm_print_condition (FILE *stream)
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/* Globally reserved letters: acln
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Puncutation letters currently used: @_|?().!#
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Lower case letters currently used: bcdefhimpqtvwxyz
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Upper case letters currently used: ABCDFGHJKLMNOPQRSTU
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Upper case letters currently used: ABCDEFGHIJKLMNOPQRSTU
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Letters previously used, but now deprecated/obsolete: sVWXYZ.
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Note that the global reservation for 'c' is only for CONSTANT_ADDRESS_P.
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@ -24134,11 +24156,12 @@ arm_print_operand (FILE *stream, rtx x, int code)
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}
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return;
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/* To print the memory operand with "Ux" constraint. Based on the rtx_code
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the memory operands output looks like following.
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/* To print the memory operand with "Ux" or "Uj" constraint. Based on the
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rtx_code the memory operands output looks like following.
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1. [Rn], #+/-<imm>
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2. [Rn, #+/-<imm>]!
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3. [Rn]. */
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3. [Rn, #+/-<imm>]
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4. [Rn]. */
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case 'E':
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{
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rtx addr;
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@ -24173,6 +24196,16 @@ arm_print_operand (FILE *stream, rtx x, int code)
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asm_fprintf (stream, ", #%wd]!",INTVAL (postinc_reg));
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}
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}
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else if (code == PLUS)
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{
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rtx base = XEXP (addr, 0);
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rtx index = XEXP (addr, 1);
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gcc_assert (REG_P (base) && CONST_INT_P (index));
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HOST_WIDE_INT offset = INTVAL (index);
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asm_fprintf (stream, "[%r, #%wd]", REGNO (base), offset);
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}
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else
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{
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gcc_assert (REG_P (addr));
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@ -33548,4 +33581,17 @@ arm_mode_base_reg_class (machine_mode mode)
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struct gcc_target targetm = TARGET_INITIALIZER;
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bool
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arm_mve_mode_and_operands_type_check (machine_mode mode, rtx op0, rtx op1)
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{
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if (!(TARGET_HAVE_MVE || TARGET_HAVE_MVE_FLOAT))
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return true;
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else if (mode == E_BFmode)
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return false;
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else if ((s_register_operand (op0, mode) && MEM_P (op1))
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|| (s_register_operand (op1, mode) && MEM_P (op0)))
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return false;
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return true;
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}
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#include "gt-arm.h"
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@ -452,6 +452,13 @@
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(and (match_code "mem")
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(match_test "TARGET_32BIT && arm_coproc_mem_operand (op, FALSE)")))
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(define_memory_constraint "Uj"
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"@internal
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In ARM/Thumb-2 state an VFP load/store address which does not support
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writeback at all (eg vldr.16)."
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(and (match_code "mem")
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(match_test "TARGET_32BIT && arm_coproc_mem_operand_no_writeback (op)")))
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(define_memory_constraint "Uy"
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"@internal
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In ARM/Thumb-2 state a valid iWMMX load/store address."
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@ -387,6 +387,20 @@
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(set_attr "arch" "t2,any,any,any,a,t2,any,any,any,any,any,any")]
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)
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(define_insn "*mov_load_vfp_hf16"
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[(set (match_operand:HF 0 "s_register_operand" "=t")
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(match_operand:HF 1 "memory_operand" "Uj"))]
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"TARGET_HAVE_MVE_FLOAT"
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"vldr.16\\t%0, %E1"
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)
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(define_insn "*mov_store_vfp_hf16"
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[(set (match_operand:HF 0 "memory_operand" "=Uj")
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(match_operand:HF 1 "s_register_operand" "t"))]
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"TARGET_HAVE_MVE_FLOAT"
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"vstr.16\\t%1, %E0"
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)
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;; HFmode and BFmode moves
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(define_insn "*mov<mode>_vfp_<mode>16"
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@ -396,6 +410,8 @@
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" m,r,t,r,r,t,Dv,Um,t, F"))]
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"TARGET_32BIT
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&& TARGET_VFP_FP16INST
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&& arm_mve_mode_and_operands_type_check (<MODE>mode, operands[0],
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operands[1])
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&& (s_register_operand (operands[0], <MODE>mode)
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|| s_register_operand (operands[1], <MODE>mode))"
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{
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@ -414,15 +430,9 @@
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case 6: /* S register from immediate. */
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return \"vmov.f16\\t%0, %1\t%@ __<fporbf>\";
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case 7: /* S register from memory. */
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if (TARGET_HAVE_MVE)
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return \"vldr.16\\t%0, %A1\";
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else
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return \"vld1.16\\t{%z0}, %A1\";
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return \"vld1.16\\t{%z0}, %A1\";
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case 8: /* Memory from S register. */
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if (TARGET_HAVE_MVE)
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return \"vstr.16\\t%1, %A0\";
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else
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return \"vst1.16\\t{%z1}, %A0\";
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return \"vst1.16\\t{%z1}, %A0\";
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case 9: /* ARM register from constant. */
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{
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long bits;
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@ -0,0 +1,17 @@
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/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */
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/* { dg-add-options arm_v8_1m_mve_fp } */
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/* { dg-additional-options "-O2" } */
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void
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fn1 (__fp16 *pSrc)
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{
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__fp16 high;
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__fp16 *pDst = 0;
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unsigned i;
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for (i = 0;; i++)
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if (pSrc[i])
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pDst[i] = high;
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}
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/* { dg-final { scan-assembler {vldr\.16\ts[0-9]+, \[r[0-9]+\]\n} } } */
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/* { dg-final { scan-assembler {vstr\.16\ts[0-9]+, \[r[0-9]+\]\n} } } */
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