2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com>
* config/s390/s390.md (*insv<mode>_reg_extimm): Removed. (*insv_h_di_reg_extimm): New insn. (*insv_l<mode>_reg_extimm): New insn. From-SVN: r143786
This commit is contained in:
parent
9e8be1e49e
commit
9fec758df2
@ -1,10 +1,16 @@
|
||||
Hariharan Sandanagobalane <hariharan@picochip.com>
|
||||
2009-01-30 Wolfgang Gellerich <gellerich@de,ibm.com>
|
||||
|
||||
* config/s390/s390.md (*insv<mode>_reg_extimm): Removed.
|
||||
(*insv_h_di_reg_extimm): New insn.
|
||||
(*insv_l<mode>_reg_extimm): New insn.
|
||||
|
||||
2009-01-30 Hariharan Sandanagobalane <hariharan@picochip.com>
|
||||
|
||||
* config/picochip/picochip.c (flag_conserve_stack): set
|
||||
PARAM_LARGE_STACK_FRAME and PARAM_STACK_FRAME_GROWTH to zero under
|
||||
fconserve-stack. Reduce call-overhead used by inliner.
|
||||
|
||||
Hariharan Sandanagobalane <hariharan@picochip.com>
|
||||
2009-01-30 Hariharan Sandanagobalane <hariharan@picochip.com>
|
||||
|
||||
PR/38157
|
||||
* common.opt (flag_conserve_stack): Initialised to zero.
|
||||
|
@ -3378,27 +3378,28 @@
|
||||
[(set_attr "op_type" "RI")
|
||||
(set_attr "z10prop" "z10_super_E1")])
|
||||
|
||||
; Update the left-most 32 bit of a DI.
|
||||
(define_insn "*insv_h_di_reg_extimm"
|
||||
[(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
|
||||
(const_int 32)
|
||||
(const_int 0))
|
||||
(match_operand:DI 1 "const_int_operand" "n"))]
|
||||
"TARGET_EXTIMM"
|
||||
"iihf\t%0,%o1"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "z10prop" "z10_fwd_E1")])
|
||||
|
||||
(define_insn "*insv<mode>_reg_extimm"
|
||||
; Update the right-most 32 bit of a DI, or the whole of a SI.
|
||||
(define_insn "*insv_l<mode>_reg_extimm"
|
||||
[(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
|
||||
(const_int 32)
|
||||
(match_operand 1 "const_int_operand" "n"))
|
||||
(match_operand:P 2 "const_int_operand" "n"))]
|
||||
"TARGET_EXTIMM
|
||||
&& INTVAL (operands[1]) >= 0
|
||||
&& INTVAL (operands[1]) < BITS_PER_WORD
|
||||
&& INTVAL (operands[1]) % 32 == 0"
|
||||
{
|
||||
switch (BITS_PER_WORD - INTVAL (operands[1]))
|
||||
{
|
||||
case 64: return "iihf\t%0,%o2"; break;
|
||||
case 32: return "iilf\t%0,%o2"; break;
|
||||
default: gcc_unreachable();
|
||||
}
|
||||
}
|
||||
&& BITS_PER_WORD - INTVAL (operands[1]) == 32"
|
||||
"iilf\t%0,%o2"
|
||||
[(set_attr "op_type" "RIL")
|
||||
(set_attr "z10prop" "z10_fwd_E1")])
|
||||
|
||||
(set_attr "z10prop" "z10_fwd_A1")])
|
||||
|
||||
;
|
||||
; extendsidi2 instruction pattern(s).
|
||||
|
Loading…
Reference in New Issue
Block a user