i386: Introduce V2QImode vectorized arithmetic [PR103861]
This patch adds basic V2QImode infrastructure and V2QImode arithmetic
operations (plus, minus and neg). The patched compiler can emit SSE
vectorized QImode operations (e.g. PADDB) with partial QImode vector,
and also synthesized double HI/LO QImode operations with integer registers.
The testcase:
typedef char __v2qi __attribute__ ((__vector_size__ (2)));
__v2qi plus (__v2qi a, __v2qi b) { return a + b; };
compiles with -O2 to:
movl %edi, %edx
movl %esi, %eax
addb %sil, %dl
addb %ah, %dh
movl %edx, %eax
ret
which is much better than what the unpatched compiler produces:
movl %edi, %eax
movl %esi, %edx
xorl %ecx, %ecx
movb %dil, %cl
movsbl %dh, %edx
movsbl %ah, %eax
addl %edx, %eax
addb %sil, %cl
movb %al, %ch
movl %ecx, %eax
ret
The V2QImode vectorization does not require vector registers, so it can
be enabled by default also for 32-bit targets without SSE.
The patch also enables vectorized V2QImode sign/zero extends.
2021-12-30 Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog:
PR target/103861
* config/i386/i386.h (VALID_SSE2_REG_MODE): Add V2QImode.
(VALID_INT_MODE_P): Ditto.
* config/i386/i386.c (ix86_secondary_reload): Handle
V2QImode reloads from SSE register to memory.
(vector_mode_supported_p): Always return true for V2QImode.
* config/i386/i386.md (*subqi_ext<mode>_2): New insn pattern.
(*negqi_ext<mode>_2): Ditto.
* config/i386/mmx.md (movv2qi): New expander.
(movmisalignv2qi): Ditto.
(*movv2qi_internal): New insn pattern.
(*pushv2qi2): Ditto.
(negv2qi2 and splitters): Ditto.
(<plusminus:insn>v2qi3 and splitters): Ditto.
gcc/testsuite/ChangeLog:
PR target/103861
* gcc.dg/store_merging_18.c (dg-options): Add -fno-tree-vectorize.
* gcc.dg/store_merging_29.c (dg-options): Ditto.
* gcc.target/i386/pr103861.c: New test.
* gcc.target/i386/pr92658-avx512vl.c (dg-final):
Remove vpmovqb scan-assembler xfail.
* gcc.target/i386/pr92658-sse4.c (dg-final):
Remove pmovzxbq scan-assembler xfail.
* gcc.target/i386/pr92658-sse4-2.c (dg-final):
Remove pmovsxbq scan-assembler xfail.
* gcc.target/i386/warn-vect-op-2.c (dg-warning): Adjust warnings.
This commit is contained in:
Uros Bizjak
parent
6bec6e3aaa
commit
9ff206d386
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@ -19306,7 +19306,7 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
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}
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/* Require movement to gpr, and then store to memory. */
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if ((mode == HFmode || mode == HImode)
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if ((mode == HFmode || mode == HImode || mode == V2QImode)
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&& !TARGET_SSE4_1
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&& SSE_CLASS_P (rclass)
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&& !in_p && MEM_P (x))
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@ -22082,6 +22082,8 @@ ix86_vector_mode_supported_p (machine_mode mode)
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if ((TARGET_3DNOW || TARGET_MMX_WITH_SSE)
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&& VALID_MMX_REG_MODE_3DNOW (mode))
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return true;
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if (mode == V2QImode)
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return true;
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return false;
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}
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@ -1039,7 +1039,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
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|| (MODE) == V8HFmode || (MODE) == V4HFmode || (MODE) == V2HFmode \
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|| (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
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|| (MODE) == V2DImode || (MODE) == DFmode || (MODE) == HFmode)
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|| (MODE) == V2DImode || (MODE) == V2QImode || (MODE) == DFmode \
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|| (MODE) == HFmode)
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#define VALID_SSE_REG_MODE(MODE) \
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((MODE) == V1TImode || (MODE) == TImode \
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@ -1072,7 +1073,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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|| (MODE) == SDmode || (MODE) == DDmode \
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|| (MODE) == HFmode || (MODE) == HCmode \
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|| (MODE) == V2HImode || (MODE) == V2HFmode \
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|| (MODE) == V1SImode || (MODE) == V4QImode \
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|| (MODE) == V1SImode || (MODE) == V4QImode || (MODE) == V2QImode \
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|| (TARGET_64BIT \
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&& ((MODE) == TImode || (MODE) == CTImode \
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|| (MODE) == TFmode || (MODE) == TCmode \
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@ -6931,6 +6931,30 @@
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operands[4] = gen_rtx_SIGN_EXTEND (<DPWI>mode, operands[2]);
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})
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(define_insn "*subqi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(minus:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 2 "register_operand" "Q")
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(const_int 8)
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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"sub{b}\t{%h2, %h0|%h0, %h2}"
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[(set_attr "type" "alu")
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(set_attr "mode" "QI")])
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(define_insn "*subv<mode>4"
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[(set (reg:CCO FLAGS_REG)
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(eq:CCO (minus:<DWI>
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@ -10901,6 +10925,25 @@
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[(set_attr "type" "negnot")
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(set_attr "mode" "<MODE>")])
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(define_insn "*negqi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(neg:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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"neg{b}\t%h0"
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[(set_attr "type" "negnot")
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(set_attr "mode" "QI")])
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;; Negate with jump on overflow.
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(define_expand "negv<mode>3"
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[(parallel [(set (reg:CCO FLAGS_REG)
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@ -261,8 +261,8 @@
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"=r ,m ,v,v,v,m,r,v")
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(match_operand:V_32 1 "general_operand"
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"rmC,rC,C,v,m,v,v,r"))]
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"TARGET_SSE2 &&
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!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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"TARGET_SSE2
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&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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{
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@ -359,6 +359,174 @@
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DONE;
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})
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(define_expand "movv2qi"
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[(set (match_operand:V2QI 0 "nonimmediate_operand")
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(match_operand:V2QI 1 "nonimmediate_operand"))]
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""
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{
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ix86_expand_vector_move (V2QImode, operands);
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DONE;
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})
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(define_insn "*movv2qi_internal"
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[(set (match_operand:V2QI 0 "nonimmediate_operand"
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"=r,r,r,m ,v,v,v,m,r,v")
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(match_operand:V2QI 1 "general_operand"
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"r ,C,m,rC,C,v,m,v,v,r"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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{
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case TYPE_IMOV:
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if (get_attr_mode (insn) == MODE_SI)
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return "mov{l}\t{%k1, %k0|%k0, %k1}";
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else
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return "mov{w}\t{%1, %0|%0, %1}";
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case TYPE_IMOVX:
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/* movzwl is faster than movw on p2 due to partial word stalls,
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though not as fast as an aligned movl. */
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return "movz{wl|x}\t{%1, %k0|%k0, %1}";
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case TYPE_SSELOG1:
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if (satisfies_constraint_C (operands[1]))
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return standard_sse_constant_opcode (insn, operands);
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if (SSE_REG_P (operands[0]))
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return MEM_P (operands[1])
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? "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}"
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: "%vpinsrw\t{$0, %k1, %d0|%d0, %k1, 0}";
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else
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return MEM_P (operands[0])
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? "%vpextrw\t{$0, %1, %0|%0, %1, 0}"
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: "%vpextrw\t{$0, %1, %k0|%k0, %1, 0}";
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case TYPE_SSEMOV:
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return ix86_output_ssemov (insn, operands);
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default:
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gcc_unreachable ();
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}
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}
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "4,5,6,8,9")
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(const_string "sse2")
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(eq_attr "alternative" "7")
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(const_string "sse4")
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]
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(const_string "*")))
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(set (attr "type")
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(cond [(eq_attr "alternative" "6,7,8,9")
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(if_then_else (match_test "TARGET_AVX512FP16")
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(const_string "ssemov")
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(const_string "sselog1"))
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(eq_attr "alternative" "4")
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(const_string "sselog1")
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(eq_attr "alternative" "5")
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(const_string "ssemov")
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(match_test "optimize_function_for_size_p (cfun)")
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(const_string "imov")
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(and (eq_attr "alternative" "0")
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(ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
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(not (match_test "TARGET_HIMODE_MATH"))))
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(const_string "imov")
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(and (eq_attr "alternative" "1,2")
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(match_operand:V2QI 1 "aligned_operand"))
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(const_string "imov")
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(and (match_test "TARGET_MOVX")
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(eq_attr "alternative" "0,2"))
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(const_string "imovx")
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]
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(const_string "imov")))
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(set (attr "prefix")
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(cond [(eq_attr "alternative" "4,5,6,7,8,9")
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(const_string "maybe_evex")
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]
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(const_string "orig")))
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(set (attr "mode")
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(cond [(eq_attr "alternative" "6,7,8,9")
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(if_then_else (match_test "TARGET_AVX512FP16")
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(const_string "HI")
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(const_string "TI"))
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(eq_attr "alternative" "4")
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(cond [(match_test "TARGET_AVX")
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(const_string "TI")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "optimize_function_for_size_p (cfun)"))
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(const_string "V4SF")
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]
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(const_string "TI"))
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(eq_attr "alternative" "5")
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(cond [(match_test "TARGET_AVX512FP16")
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(const_string "HI")
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(match_test "TARGET_AVX")
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(const_string "TI")
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(ior (not (match_test "TARGET_SSE2"))
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(match_test "optimize_function_for_size_p (cfun)"))
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(const_string "V4SF")
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]
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(const_string "TI"))
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(eq_attr "type" "imovx")
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(const_string "SI")
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(and (eq_attr "alternative" "1,2")
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(match_operand:V2QI 1 "aligned_operand"))
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(const_string "SI")
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(and (eq_attr "alternative" "0")
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(ior (not (match_test "TARGET_PARTIAL_REG_STALL"))
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(not (match_test "TARGET_HIMODE_MATH"))))
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(const_string "SI")
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]
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(const_string "HI")))
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(set (attr "preferred_for_speed")
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(cond [(eq_attr "alternative" "8")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
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(eq_attr "alternative" "9")
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(symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
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]
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(symbol_ref "true")))])
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;; We always round up to UNITS_PER_WORD bytes.
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(define_insn "*pushv2qi2"
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[(set (match_operand:V2QI 0 "push_operand" "=X,X")
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(match_operand:V2QI 1 "nonmemory_no_elim_operand" "rC,v"))]
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""
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"* return TARGET_64BIT ? \"push{q}\t%q1\" : \"push{l}\t%k1\";
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#"
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[(set_attr "isa" "*,sse4")
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(set_attr "type" "push,multi")
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(set (attr "mode")
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(cond [(eq_attr "alternative" "0")
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(if_then_else (match_test "TARGET_64BIT")
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(const_string "DI")
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(const_string "SI"))
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(eq_attr "alternative" "1")
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(if_then_else (match_test "TARGET_AVX512FP16")
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(const_string "HI")
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(const_string "TI"))
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]
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(const_string "HI")))])
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(define_split
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[(set (match_operand:V2QI 0 "push_operand")
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(match_operand:V2QI 1 "sse_reg_operand"))]
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"TARGET_SSE4_1 && reload_completed"
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[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
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(set (match_dup 0) (match_dup 1))]
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{
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operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (V2QImode)));
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/* Preserve memory attributes. */
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operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
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})
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(define_expand "movmisalignv2qi"
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[(set (match_operand:V2QI 0 "nonimmediate_operand")
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(match_operand:V2QI 1 "nonimmediate_operand"))]
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""
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{
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ix86_expand_vector_move (V2QImode, operands);
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DONE;
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})
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(define_insn "sse_movntq"
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[(set (match_operand:DI 0 "memory_operand" "=m,m")
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(unspec:DI [(match_operand:DI 1 "register_operand" "y,r")]
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@ -1461,6 +1629,58 @@
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"TARGET_MMX_WITH_SSE"
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"operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
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(define_insn "negv2qi2"
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[(set (match_operand:V2QI 0 "register_operand" "=Q,&Yw")
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(neg:V2QI
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(match_operand:V2QI 1 "register_operand" "0,Yw")))
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(clobber (reg:CC FLAGS_REG))]
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""
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"#"
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[(set_attr "isa" "*,sse2")
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(set_attr "type" "multi")
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(set_attr "mode" "QI,TI")])
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(define_split
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[(set (match_operand:V2QI 0 "general_reg_operand")
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(neg:V2QI
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(match_operand:V2QI 1 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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[(parallel
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[(set (strict_low_part (match_dup 0))
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(neg:QI (match_dup 1)))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (zero_extract:HI (match_dup 2) (const_int 8) (const_int 8))
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(subreg:HI
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(neg:QI
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(subreg:QI
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(zero_extract:HI (match_dup 3)
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(const_int 8)
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(const_int 8)) 0)) 0))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[3] = gen_lowpart (HImode, operands[1]);
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operands[2] = gen_lowpart (HImode, operands[0]);
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operands[1] = gen_lowpart (QImode, operands[1]);
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operands[0] = gen_lowpart (QImode, operands[0]);
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})
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(define_split
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[(set (match_operand:V2QI 0 "sse_reg_operand")
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(neg:V2QI
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(match_operand:V2QI 1 "sse_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0)
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(minus:V4QI (match_dup 0) (match_dup 1)))]
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{
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operands[2] = CONST0_RTX (V4QImode);
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operands[1] = gen_lowpart (V4QImode, operands[1]);
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operands[0] = gen_lowpart (V4QImode, operands[0]);
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})
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(define_expand "mmx_<insn><mode>3"
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[(set (match_operand:MMXMODEI8 0 "register_operand")
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(plusminus:MMXMODEI8
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@ -1515,6 +1735,66 @@
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(set_attr "type" "sseadd")
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(set_attr "mode" "TI")])
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(define_insn "<insn>v2qi3"
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[(set (match_operand:V2QI 0 "register_operand" "=Q,x,Yw")
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(plusminus:V2QI
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(match_operand:V2QI 1 "register_operand" "<comm>0,0,Yw")
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(match_operand:V2QI 2 "register_operand" "Q,x,Yw")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
""
|
||||
"#"
|
||||
[(set_attr "isa" "*,sse2_noavx,avx")
|
||||
(set_attr "type" "multi,sseadd,sseadd")
|
||||
(set_attr "mode" "QI,TI,TI")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:V2QI 0 "general_reg_operand")
|
||||
(plusminus:V2QI
|
||||
(match_operand:V2QI 1 "general_reg_operand")
|
||||
(match_operand:V2QI 2 "general_reg_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"reload_completed"
|
||||
[(parallel
|
||||
[(set (strict_low_part (match_dup 0))
|
||||
(plusminus:QI (match_dup 1) (match_dup 2)))
|
||||
(clobber (reg:CC FLAGS_REG))])
|
||||
(parallel
|
||||
[(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
|
||||
(subreg:HI
|
||||
(plusminus:QI
|
||||
(subreg:QI
|
||||
(zero_extract:HI (match_dup 4)
|
||||
(const_int 8)
|
||||
(const_int 8)) 0)
|
||||
(subreg:QI
|
||||
(zero_extract:HI (match_dup 5)
|
||||
(const_int 8)
|
||||
(const_int 8)) 0)) 0))
|
||||
(clobber (reg:CC FLAGS_REG))])]
|
||||
{
|
||||
operands[5] = gen_lowpart (HImode, operands[2]);
|
||||
operands[4] = gen_lowpart (HImode, operands[1]);
|
||||
operands[3] = gen_lowpart (HImode, operands[0]);
|
||||
operands[2] = gen_lowpart (QImode, operands[2]);
|
||||
operands[1] = gen_lowpart (QImode, operands[1]);
|
||||
operands[0] = gen_lowpart (QImode, operands[0]);
|
||||
})
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:V2QI 0 "sse_reg_operand")
|
||||
(plusminus:V2QI
|
||||
(match_operand:V2QI 1 "sse_reg_operand")
|
||||
(match_operand:V2QI 2 "sse_reg_operand")))
|
||||
(clobber (reg:CC FLAGS_REG))]
|
||||
"TARGET_SSE2 && reload_completed"
|
||||
[(set (match_dup 0)
|
||||
(plusminus:V4QI (match_dup 1) (match_dup 2)))]
|
||||
{
|
||||
operands[2] = gen_lowpart (V4QImode, operands[2]);
|
||||
operands[1] = gen_lowpart (V4QImode, operands[1]);
|
||||
operands[0] = gen_lowpart (V4QImode, operands[0]);
|
||||
})
|
||||
|
||||
(define_expand "mmx_<insn><mode>3"
|
||||
[(set (match_operand:MMXMODE12 0 "register_operand")
|
||||
(sat_plusminus:MMXMODE12
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* PR tree-optimization/83843 */
|
||||
/* { dg-do run } */
|
||||
/* { dg-options "-O2 -fdump-tree-store-merging" } */
|
||||
/* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-store-merging" } */
|
||||
/* { dg-final { scan-tree-dump-times "Merging successful" 3 "store-merging" { target { store_merge && { ! arm*-*-* } } } } } */
|
||||
|
||||
__attribute__((noipa)) void
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* PR tree-optimization/88709 */
|
||||
/* { dg-do run { target int32 } } */
|
||||
/* { dg-require-effective-target store_merge } */
|
||||
/* { dg-options "-O2 -fdump-tree-store-merging-details" } */
|
||||
/* { dg-options "-O2 -fno-tree-vectorize -fdump-tree-store-merging-details" } */
|
||||
/* { dg-final { scan-tree-dump "New sequence of 3 stores to replace old one of 6 stores" "store-merging" { target { le && { ! arm*-*-* } } } } } */
|
||||
/* { dg-final { scan-tree-dump "New sequence of \[34] stores to replace old one of 6 stores" "store-merging" { target { be && { ! arm*-*-* } } } } } */
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
/* PR target/103861 */
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -dp" } */
|
||||
|
||||
typedef char __v2qi __attribute__ ((__vector_size__ (2)));
|
||||
|
||||
__v2qi and (__v2qi a, __v2qi b) { return a & b; };
|
||||
|
||||
__v2qi andn (__v2qi a, __v2qi b) { return a & ~b; };
|
||||
|
||||
__v2qi or (__v2qi a, __v2qi b) { return a | b; };
|
||||
|
||||
__v2qi xor (__v2qi a, __v2qi b) { return a ^ b; };
|
||||
|
||||
__v2qi not (__v2qi a) { return ~a; };
|
||||
|
||||
__v2qi plus (__v2qi a, __v2qi b) { return a + b; };
|
||||
|
||||
__v2qi minus (__v2qi a, __v2qi b) { return a - b; };
|
||||
|
||||
__v2qi neg (__v2qi a) { return -a; };
|
||||
|
||||
/* { dg-final { scan-assembler-not "insvhi" } } */
|
||||
|
|
@ -123,7 +123,7 @@ truncdb_128 (v16qi * dst, v4si * __restrict src)
|
|||
|
||||
/* { dg-final { scan-assembler-times "vpmovqd" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovqw" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovqb\[ \t]*%ymm" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovqb\[ \t]*%xmm" 1 { xfail *-*-* } } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovqb\[ \t]*%ymm" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovqb\[ \t]*%xmm" 1 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovdw" 2 } } */
|
||||
/* { dg-final { scan-assembler-times "vpmovdb" 2 } } */
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ bar_s8_s64 (v2di * dst, v16qi src)
|
|||
dst[0] = *(v2di *) tem;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "pmovsxbq" 2 { xfail *-*-* } } } */
|
||||
/* { dg-final { scan-assembler-times "pmovsxbq" 2 } } */
|
||||
|
||||
void
|
||||
foo_s16_s32 (v4si * dst, v8hi * __restrict src)
|
||||
|
|
|
|||
|
|
@ -81,7 +81,7 @@ bar_u8_u64 (v2di * dst, v16qi src)
|
|||
dst[0] = *(v2di *) tem;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler-times "pmovzxbq" 2 { xfail *-*-* } } } */
|
||||
/* { dg-final { scan-assembler-times "pmovzxbq" 2 } } */
|
||||
|
||||
void
|
||||
foo_u16_u32 (v4si * dst, v8hi * __restrict src)
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@ int main (int argc, char *argv[])
|
|||
argc, 1, 15, 38, 12, -1, argc, 2};
|
||||
vector (16, signed char) res[] =
|
||||
{
|
||||
v0 + v1, /* { dg-warning "expanded in parallel" } */
|
||||
v0 - v1, /* { dg-warning "expanded in parallel" } */
|
||||
v0 + v1, /* { dg-warning "expanded piecewise" } */
|
||||
v0 - v1, /* { dg-warning "expanded piecewise" } */
|
||||
v0 > v1, /* { dg-warning "expanded piecewise" } */
|
||||
v0 & v1, /* { dg-warning "expanded in parallel" } */
|
||||
__builtin_shuffle (v0, v1), /* { dg-warning "expanded piecewise" } */
|
||||
|
|
|
|||
Loading…
Reference in New Issue