pdp11-protos.h (pdp11_cannot_change_mode_class, [...]): Declare.
* config/pdp11/pdp11-protos.h (pdp11_cannot_change_mode_class, pdp11_secondary_memory_needed): Declare. * config/pdp11/predicates.md (float_operand): New predicate. * config/pdp11/pdp11.md (RETVAL_REGNUM): New constant. (cbranchdf4, movdf): Change predicate. (movsf): Handle FPU register case. (truncdfsf2, extendsfdf2): Add FPU register case. * config/pdp11/pdp11.c (TARGET_SECONDARY_RELOAD, TARGET_REGISTER_MOVE_COST, TARGET_PREFERRED_RELOAD_CLASS, TARGET_PREFERRED_OUTPUT_RELOAD_CLASS): Define. (pdp11_register_move_cost): Update cost matrix. (pdp11_cannot_change_mode_class, pdp11_preferred_reload_class, pdp11_preferred_output_reload_class, pdp11_secondary_reload, pdp11_secondary_memory_needed): New function. (pdp11_return_in_memory): Add other float types. * config/pdp11/pdp11.h (HARD_REGNO_MODE_OK): Add other float types. (SECONDARY_MEMORY_NEEDED, CANNOT_CHANGE_MODE_CLASS): Define. (PREFERRED_RELOAD_CLASS, SECONDARY_RELOAD_CLASS, REGISTER_MOVE_COST): Delete. (BASE_RETURN_VALUE_REG): Add other float types. From-SVN: r166060
This commit is contained in:
Paul Koning
Paul Koning
parent
1e4bf85b80
commit
a01c666cc6
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@ -1,3 +1,27 @@
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2010-10-29 Paul Koning <pkoning@equallogic.com>
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* config/pdp11/pdp11-protos.h (pdp11_cannot_change_mode_class,
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pdp11_secondary_memory_needed): Declare.
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* config/pdp11/predicates.md (float_operand): New predicate.
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* config/pdp11/pdp11.md (RETVAL_REGNUM): New constant.
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(cbranchdf4, movdf): Change predicate.
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(movsf): Handle FPU register case.
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(truncdfsf2, extendsfdf2): Add FPU register case.
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* config/pdp11/pdp11.c (TARGET_SECONDARY_RELOAD,
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TARGET_REGISTER_MOVE_COST, TARGET_PREFERRED_RELOAD_CLASS,
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TARGET_PREFERRED_OUTPUT_RELOAD_CLASS): Define.
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(pdp11_register_move_cost): Update cost matrix.
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(pdp11_cannot_change_mode_class, pdp11_preferred_reload_class,
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pdp11_preferred_output_reload_class, pdp11_secondary_reload,
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pdp11_secondary_memory_needed): New function.
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(pdp11_return_in_memory): Add other float types.
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* config/pdp11/pdp11.h (HARD_REGNO_MODE_OK): Add other float
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types.
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(SECONDARY_MEMORY_NEEDED, CANNOT_CHANGE_MODE_CLASS): Define.
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(PREFERRED_RELOAD_CLASS, SECONDARY_RELOAD_CLASS,
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REGISTER_MOVE_COST): Delete.
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(BASE_RETURN_VALUE_REG): Add other float types.
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2010-10-29 Nick Clifton<nickc@redhat.com>
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* doc/invoke.texi: Document -mam34 and -mtune options.
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@ -31,7 +31,11 @@ extern const char *output_move_quad (rtx *);
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extern const char *output_block_move (rtx *);
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extern const char *output_jump (enum rtx_code, int, int);
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extern void print_operand_address (FILE *, rtx);
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extern int pdp11_register_move_cost (enum reg_class, enum reg_class);
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extern bool pdp11_cannot_change_mode_class (enum machine_mode,
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enum machine_mode, enum reg_class);
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extern bool pdp11_secondary_memory_needed (reg_class_t, reg_class_t,
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enum machine_mode);
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#endif /* RTX_CODE */
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extern void output_ascii (FILE *, const char *, int);
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@ -216,7 +216,17 @@ static const struct default_options pdp11_option_optimization_table[] =
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#undef TARGET_TRAMPOLINE_INIT
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#define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
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struct gcc_target targetm = TARGET_INITIALIZER;
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#undef TARGET_SECONDARY_RELOAD
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#define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
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#undef TARGET_REGISTER_MOVE_COST
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#define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
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#undef TARGET_PREFERRED_RELOAD_CLASS
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#define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
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#undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
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#define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
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/* Implement TARGET_HANDLE_OPTION. */
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@ -417,7 +427,7 @@ pdp11_output_function_epilogue (FILE *stream, HOST_WIDE_INT size)
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/* get ACs */
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for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
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if (df_regs_ever_live_p (i) && call_used_regs[i])
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if (df_regs_ever_live_p (i) && ! call_used_regs[i])
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via_ac = i;
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for (i = AC5_REGNUM; i >= AC0_REGNUM; i--)
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@ -1054,22 +1064,23 @@ static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] =
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/* NO MUL GEN LFPU NLFPU FPU ALL */
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/* NO */ { 0, 0, 0, 0, 0, 0, 0},
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/* MUL */ { 0, 2, 2, 10, 22, 22, 22},
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/* GEN */ { 0, 2, 2, 10, 22, 22, 22},
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/* LFPU */ { 0, 10, 10, 2, 2, 2, 10},
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/* NLFPU */ { 0, 22, 22, 2, 2, 2, 22},
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/* FPU */ { 0, 22, 22, 2, 2, 2, 22},
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/* ALL */ { 0, 22, 22, 10, 22, 22, 22}
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/* MUL */ { 0, 2, 2, 22, 22, 22, 22},
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/* GEN */ { 0, 2, 2, 22, 22, 22, 22},
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/* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
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/* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
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/* FPU */ { 0, 22, 22, 2, 10, 10, 22},
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/* ALL */ { 0, 22, 22, 22, 22, 22, 22}
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} ;
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/* -- note that some moves are tremendously expensive,
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because they require lots of tricks! do we have to
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charge the costs incurred by secondary reload class
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-- as we do here with 22 -- or not ? */
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-- as we do here with 10 -- or not ? */
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int
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pdp11_register_move_cost (enum reg_class c1, enum reg_class c2)
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static int
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pdp11_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
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reg_class_t c1, reg_class_t c2)
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{
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return move_costs[(int)c1][(int)c2];
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}
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@ -1634,6 +1645,108 @@ legitimate_const_double_p (rtx address)
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return 0;
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}
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/* Implement CANNOT_CHANGE_MODE_CLASS. */
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bool
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pdp11_cannot_change_mode_class (enum machine_mode from,
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enum machine_mode to,
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enum reg_class rclass)
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{
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/* Also, FPU registers contain a whole float value and the parts of
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it are not separately accessible.
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So we disallow all mode changes involving FPRs. */
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if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to))
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return true;
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return reg_classes_intersect_p (FPU_REGS, rclass);
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}
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/* TARGET_PREFERRED_RELOAD_CLASS
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Given an rtx X being reloaded into a reg required to be
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in class CLASS, return the class of reg to actually use.
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In general this is just CLASS; but on some machines
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in some cases it is preferable to use a more restrictive class.
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loading is easier into LOAD_FPU_REGS than FPU_REGS! */
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static reg_class_t
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pdp11_preferred_reload_class (rtx x, reg_class_t class)
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{
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if (class == FPU_REGS)
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return LOAD_FPU_REGS;
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if (class == ALL_REGS)
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{
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if (FLOAT_MODE_P (GET_MODE (x)))
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return LOAD_FPU_REGS;
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else
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return GENERAL_REGS;
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}
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return class;
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}
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/* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
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Given an rtx X being reloaded into a reg required to be
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in class CLASS, return the class of reg to actually use.
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In general this is just CLASS; but on some machines
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in some cases it is preferable to use a more restrictive class.
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loading is easier into LOAD_FPU_REGS than FPU_REGS! */
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static reg_class_t
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pdp11_preferred_output_reload_class (rtx x, reg_class_t class)
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{
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if (class == FPU_REGS)
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return LOAD_FPU_REGS;
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if (class == ALL_REGS)
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{
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if (FLOAT_MODE_P (GET_MODE (x)))
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return LOAD_FPU_REGS;
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else
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return GENERAL_REGS;
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}
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return class;
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}
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/* TARGET_SECONDARY_RELOAD.
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FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
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intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
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can be loade/stored directly. */
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reg_class_t
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pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
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rtx x,
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reg_class_t reload_class,
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enum machine_mode reload_mode ATTRIBUTE_UNUSED,
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secondary_reload_info *sri ATTRIBUTE_UNUSED)
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{
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if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
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REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
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return NO_REGS;
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return LOAD_FPU_REGS;
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}
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/* Target routine to check if register to register move requires memory.
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The answer is yes if we're going between general register and FPU
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registers. The mode doesn't matter in making this check.
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*/
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bool
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pdp11_secondary_memory_needed (reg_class_t c1, reg_class_t c2,
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enum machine_mode mode ATTRIBUTE_UNUSED)
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{
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int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS ||
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c1 == FPU_REGS);
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int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS ||
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c2 == FPU_REGS);
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return (fromfloat != tofloat);
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}
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/* A copy of output_addr_const modified for pdp11 expression syntax.
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output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
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use, and for debugging output, which we don't support with this port either.
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@ -1751,7 +1864,7 @@ pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
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ac0 if DFmode and FPU present - compatibility problem with
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libraries for non-floating point.... */
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return (TYPE_MODE (type) == DImode
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|| (TYPE_MODE (type) == DFmode && ! TARGET_AC0));
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|| (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0));
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}
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/* Worker function for TARGET_FUNCTION_VALUE.
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@ -1854,3 +1967,5 @@ pdp11_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
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? GET_MODE_SIZE (mode)
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: int_size_in_bytes (type));
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}
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struct gcc_target targetm = TARGET_INITIALIZER;
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@ -215,15 +215,19 @@ extern const struct real_format pdp11_d_format;
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
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On the pdp, the cpu registers can hold any mode - check alignment
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On the pdp, the cpu registers can hold any mode other than float
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(because otherwise we may end up being asked to move from CPU to FPU
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register, which isn't a valid operation on the PDP11).
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For CPU registers, check alignment.
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FPU can only hold DF - simplifies life!
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FPU accepts SF and DF but actually holds a DF - simplifies life!
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*/
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#define HARD_REGNO_MODE_OK(REGNO, MODE) \
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(((REGNO) <= PC_REGNUM)? \
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((GET_MODE_BITSIZE(MODE) <= 16) \
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|| (GET_MODE_BITSIZE(MODE) >= 32 && !((REGNO) & 1))) \
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:(MODE) == DFmode)
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|| (GET_MODE_BITSIZE(MODE) >= 32 && \
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!((REGNO) & 1) && !FLOAT_MODE_P (MODE))) \
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:FLOAT_MODE_P (MODE))
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/* Value is 1 if it is a good idea to tie two pseudo registers
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@ -322,18 +326,9 @@ enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REG
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#define IRA_COVER_CLASSES { GENERAL_REGS, FPU_REGS, LIM_REG_CLASSES }
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/* Given an rtx X being reloaded into a reg required to be
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in class CLASS, return the class of reg to actually use.
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In general this is just CLASS; but on some machines
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in some cases it is preferable to use a more restrictive class.
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loading is easier into LOAD_FPU_REGS than FPU_REGS! */
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#define PREFERRED_RELOAD_CLASS(X,CLASS) \
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(((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS)
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#define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \
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(((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS)
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/* Hook for testing if memory is needed for moving between registers. */
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#define SECONDARY_MEMORY_NEEDED(class1, class2, m) \
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pdp11_secondary_memory_needed (class1, class2, m)
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/* Return the maximum number of consecutive registers
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needed to represent mode MODE in a register of class CLASS. */
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@ -343,6 +338,8 @@ loading is easier into LOAD_FPU_REGS than FPU_REGS! */
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1 \
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)
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#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
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pdp11_cannot_change_mode_class (FROM, TO, CLASS)
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/* Stack layout; function entry, exit and calling. */
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@ -386,7 +383,7 @@ extern int current_first_parm_offset;
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If the precise function being called is known, FUNC is its FUNCTION_DECL;
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otherwise, FUNC is 0. */
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#define BASE_RETURN_VALUE_REG(MODE) \
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((MODE) == DFmode ? 8 : 0)
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(FLOAT_MODE_P (MODE) ? AC0_REGNUM : RETVAL_REGNUM)
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/* 1 if N is a possible register number for function argument passing.
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- not used on pdp */
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@ -674,10 +671,6 @@ extern int may_call_alloca;
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/* #define NO_FUNCTION_CSE */
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/* cost of moving one register class to another */
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#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
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pdp11_register_move_cost (CLASS1, CLASS2)
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/* Tell emit-rtl.c how to initialize special values on a per-function base. */
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extern struct rtx_def *cc0_reg_rtx;
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@ -25,6 +25,7 @@
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(define_constants
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[
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;; Register numbers
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(RETVAL_REGNUM 0)
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(FRAME_POINTER_REGNUM 5)
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(STACK_POINTER_REGNUM 6)
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(PC_REGNUM 7)
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@ -196,7 +197,7 @@
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(define_expand "cbranchdf4"
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[(set (cc0)
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(compare (match_operand:DF 1 "general_operand")
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(match_operand:DF 2 "general_operand")))
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(match_operand:DF 2 "register_or_const0_operand")))
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(set (pc)
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(if_then_else (match_operator 0 "ordered_comparison_operator"
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[(cc0) (const_int 0)])
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@ -318,11 +319,9 @@
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}"
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[(set_attr "length" "2,4,4,6")])
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;; do we have to supply all these moves? e.g. to
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;; NO_LOAD_FPU_REGs ?
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(define_insn "movdf"
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[(set (match_operand:DF 0 "general_operand" "=a,fR,a,Q,g")
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(match_operand:DF 1 "general_operand" "fFR,a,Q,a,g"))]
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[(set (match_operand:DF 0 "float_operand" "=a,fR,a,Q,g")
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(match_operand:DF 1 "float_operand" "fFR,a,Q,a,g"))]
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"TARGET_FPU"
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"* if (which_alternative ==0 || which_alternative == 2)
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return \"ldd %1, %0\";
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@ -334,11 +333,17 @@
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[(set_attr "length" "2,2,10,10,32")])
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(define_insn "movsf"
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[(set (match_operand:SF 0 "general_operand" "=g,r,g")
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(match_operand:SF 1 "general_operand" "r,rmF,g"))]
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[(set (match_operand:SF 0 "float_operand" "=a,fR,a,Q,g")
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(match_operand:SF 1 "float_operand" "fFR,a,Q,a,g"))]
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"TARGET_FPU"
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"* return output_move_double (operands);"
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[(set_attr "length" "16,16,16")])
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"* if (which_alternative ==0 || which_alternative == 2)
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return \"{ldcfd|movof} %1, %0\";
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else if (which_alternative == 1 || which_alternative == 3)
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return \"{stcdf|movfo} %1, %0\";
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else
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return output_move_double (operands); "
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;; just a guess..
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[(set_attr "length" "2,2,10,10,16")])
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;; maybe fiddle a bit with move_ratio, then
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;; let constraints only accept a register ...
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@ -386,15 +391,11 @@
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;;- truncation instructions
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(define_insn "truncdfsf2"
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[(set (match_operand:SF 0 "general_operand" "=r,R,Q")
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(float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))]
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[(set (match_operand:SF 0 "general_operand" "=f,R,Q")
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(float_truncate:SF (match_operand:DF 1 "register_operand" "f,a,a")))]
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"TARGET_FPU"
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"* if (which_alternative ==0)
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{
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output_asm_insn(\"{stcdf|movfo} %1, -(sp)\", operands);
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output_asm_insn(\"mov (sp)+, %0\", operands);
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operands[0] = gen_rtx_REG (HImode, REGNO (operands[0])+1);
|
||||
output_asm_insn(\"mov (sp)+, %0\", operands);
|
||||
return \"\";
|
||||
}
|
||||
else if (which_alternative == 1)
|
||||
|
|
@ -402,7 +403,7 @@
|
|||
else
|
||||
return \"{stcdf|movfo} %1, %0\";
|
||||
"
|
||||
[(set_attr "length" "6,2,4")])
|
||||
[(set_attr "length" "0,2,4")])
|
||||
|
||||
|
||||
(define_expand "truncsihi2"
|
||||
|
|
@ -439,14 +440,14 @@
|
|||
;;- sign extension instructions
|
||||
|
||||
(define_insn "extendsfdf2"
|
||||
[(set (match_operand:DF 0 "register_operand" "=a,a,a")
|
||||
(float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))]
|
||||
[(set (match_operand:DF 0 "register_operand" "=f,a,a")
|
||||
(float_extend:DF (match_operand:SF 1 "general_operand" "f,R,Q")))]
|
||||
"TARGET_FPU"
|
||||
"@
|
||||
mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0
|
||||
/* nothing */
|
||||
{ldcfd|movof} %1, %0
|
||||
{ldcfd|movof} %1, %0"
|
||||
[(set_attr "length" "4,2,4")])
|
||||
[(set_attr "length" "0,2,4")])
|
||||
|
||||
;; does movb sign extend in register-to-register move?
|
||||
(define_insn "extendqihi2"
|
||||
|
|
@ -856,6 +857,7 @@
|
|||
}"
|
||||
[(set_attr "length" "4,8,8,12,4,4,8,6,6,12")])
|
||||
|
||||
;; FIXME This definition is wrong, PR/41822
|
||||
(define_insn "andhi3"
|
||||
[(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
|
||||
(and:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
|
||||
|
|
|
|||
|
|
@ -35,3 +35,12 @@
|
|||
sh = INTVAL (op);
|
||||
return (abs (sh) > 1 && abs (sh) <= 4);
|
||||
})
|
||||
|
||||
;; Accept anything general-operand accepts, except that registers must
|
||||
;; be FPU registers.
|
||||
(define_predicate "float_operand"
|
||||
(if_then_else (match_code "reg")
|
||||
(ior
|
||||
(match_test "REGNO_REG_CLASS (REGNO (op)) == LOAD_FPU_REGS")
|
||||
(match_test "REGNO_REG_CLASS (REGNO (op)) == NO_LOAD_FPU_REGS"))
|
||||
(match_test "general_operand (op, mode)")))
|
||||
|
|
|
|||
Loading…
Reference in New Issue