i386.md (isa): Add sse2, sse2_noavx, sse3, sse4 and sse4_noavx.
* config/i386/i386.md (isa): Add sse2, sse2_noavx, sse3,
sse4 and sse4_noavx.
(enabled): Handle sse2, sse2_noavx, sse3, sse4 and sse4_noavx.
(*pushdf_rex64): Change Y2 register constraint to x.
(*movdf_internal_rex64): Ditto.
(*zero_extendsidi2_rex64): Ditto.
(*movdi_internal): Change Y2 register constraint to x
and update "isa" attribute.
(*pushdf): Ditto.
(*movdf internal): Ditto.
(zero_extendsidi2_1): Ditto.
(*truncdfdf_mixed): Ditto.
(*truncxfdf2_mixed): Ditto.
* config/i386/mmx.md (*mov<mode>_internal_rex64): Change Y2
register constraint to x.
(*movv2sf_internal_rex64): Ditto.
(*mov<mode>_internal): Change Y2 register constraint to x
and add "isa" attribute.
(*movv2sf_internal): Ditto.
(*vec_extractv2si_1): Ditto.
* config/i386/sse.md ("vec_set<mode>_0): Change Y2 and Y4 register
constraints to x and update "isa" attribute.
(*vec_interleave_highv2df): Change Y3 registerconstraint
to x and update "isa" attribute.
(*vec_interleave_lowv2df): Ditto.
(*vec_concatv2df): Change Y2 register constraint to x and
update "isa" attribute.
(sse2_loadld): Ditto.
(*vec_extractv2di_1): Ditto.
(*vec_dupv4si): Ditto.
(*vec_dupv2di): Ditto.
(*vec_concatv4si): Ditto.
(vec_concatv2di): Ditto.
* config/i386/constraints.md (Y2): Remove.
(Y3): Ditto.
(Y4): Ditto.
From-SVN: r178073
This commit is contained in:
Uros Bizjak
parent
aa13dc3c93
commit
a02f398da4
@ -1,3 +1,42 @@
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2011-08-25 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.md (isa): Add sse2, sse2_noavx, sse3,
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sse4 and sse4_noavx.
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(enabled): Handle sse2, sse2_noavx, sse3, sse4 and sse4_noavx.
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(*pushdf_rex64): Change Y2 register constraint to x.
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(*movdf_internal_rex64): Ditto.
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(*zero_extendsidi2_rex64): Ditto.
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(*movdi_internal): Change Y2 register constraint to x
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and update "isa" attribute.
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(*pushdf): Ditto.
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(*movdf internal): Ditto.
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(zero_extendsidi2_1): Ditto.
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(*truncdfdf_mixed): Ditto.
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(*truncxfdf2_mixed): Ditto.
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* config/i386/mmx.md (*mov<mode>_internal_rex64): Change Y2
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register constraint to x.
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(*movv2sf_internal_rex64): Ditto.
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(*mov<mode>_internal): Change Y2 register constraint to x
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and add "isa" attribute.
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(*movv2sf_internal): Ditto.
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(*vec_extractv2si_1): Ditto.
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* config/i386/sse.md ("vec_set<mode>_0): Change Y2 and Y4 register
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constraints to x and update "isa" attribute.
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(*vec_interleave_highv2df): Change Y3 registerconstraint
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to x and update "isa" attribute.
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(*vec_interleave_lowv2df): Ditto.
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(*vec_concatv2df): Change Y2 register constraint to x and
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update "isa" attribute.
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(sse2_loadld): Ditto.
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(*vec_extractv2di_1): Ditto.
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(*vec_dupv4si): Ditto.
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(*vec_dupv2di): Ditto.
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(*vec_concatv4si): Ditto.
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(vec_concatv2di): Ditto.
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* config/i386/constraints.md (Y2): Remove.
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(Y3): Ditto.
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(Y4): Ditto.
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2011-08-25 Bernd Schmidt <bernds@codesourcery.com>
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* regrename.c (scan_rtx_reg, scan_rtx_address, build_def_use,
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@ -18,7 +57,7 @@
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* config/avr/avr.c (reg_class_tab): Make local to
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avr_regno_reg_class. Return smallest register class available.
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2011-08-25 Georg-Johann Lay <avr@gjlay.de>
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* config/avr/avr.c (STR_PREFIX_P): New Define.
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@ -36,13 +75,11 @@
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(gen_automata_option): Check for COLLAPSE_OPTION.
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(collapse_ndfa_insn_decl): New static variable.
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(add_collapse_ndfa_insn_decl, special_decl_p): New functions.
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(find_arc): If insn is the collapse-ndfa insn, accept any arc we
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find.
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(find_arc): If insn is the collapse-ndfa insn, accept any arc we find.
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(transform_insn_regexps): Call add_collapse_ndfa_insn_decl if
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necessary. Use normal_decls_num rather than decls_num, remove
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test for special decls.
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(create_alt_states, form_ainsn_with_same_reservs): Use
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special_decl_p.
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(create_alt_states, form_ainsn_with_same_reservs): Use special_decl_p.
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(make_automaton); Likewise. Use the new advance_cycle_insn member
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of struct automaton.
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(create_composed_state): Disallow advance-cycle arcs if collapse_flag
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@ -90,8 +127,7 @@
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2011-08-24 H.J. Lu <hongjiu.lu@intel.com>
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PR target/50172
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* config/i386/i386.c (ix86_expand_builtin): Convert to Pmode if
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needed.
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* config/i386/i386.c (ix86_expand_builtin): Convert to Pmode if needed.
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2011-08-24 Richard Guenther <rguenther@suse.de>
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@ -87,9 +87,6 @@
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;; We use the Y prefix to denote any number of conditional register sets:
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;; z First SSE register.
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;; 2 SSE2 enabled
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;; 3 SSE3 enabled
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;; 4 SSE4_1 enabled
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;; i SSE2 inter-unit moves enabled
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;; m MMX inter-unit moves enabled
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;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
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@ -99,15 +96,6 @@
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(define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
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"First SSE register (@code{%xmm0}).")
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(define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE2 is enabled.")
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(define_register_constraint "Y3" "TARGET_SSE3 ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE3 is enabled.")
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(define_register_constraint "Y4" "TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE4_1 is enabled.")
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(define_register_constraint "Yi"
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"TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
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"@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
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@ -711,12 +711,19 @@
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(define_attr "movu" "0,1" (const_string "0"))
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;; Used to control the "enabled" attribute on a per-instruction basis.
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(define_attr "isa" "base,noavx,avx,bmi2"
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(define_attr "isa" "base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2"
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(const_string "base"))
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(define_attr "enabled" ""
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(cond [(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
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(cond [(eq_attr "isa" "sse2") (symbol_ref "TARGET_SSE2")
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(eq_attr "isa" "sse2_noavx")
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(symbol_ref "TARGET_SSE2 && !TARGET_AVX")
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(eq_attr "isa" "sse3") (symbol_ref "TARGET_SSE3")
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(eq_attr "isa" "sse4") (symbol_ref "TARGET_SSE4_1")
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(eq_attr "isa" "sse4_noavx")
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(symbol_ref "TARGET_SSE4_1 && !TARGET_AVX")
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(eq_attr "isa" "avx") (symbol_ref "TARGET_AVX")
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(eq_attr "isa" "noavx") (symbol_ref "!TARGET_AVX")
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(eq_attr "isa" "bmi2") (symbol_ref "TARGET_BMI2")
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]
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(const_int 1)))
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@ -2153,9 +2160,9 @@
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(define_insn "*movdi_internal"
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[(set (match_operand:DI 0 "nonimmediate_operand"
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"=r ,o ,*y,m*y,*y,*Y2,m ,*Y2,*Y2,*x,m ,*x,*x,?*Y2,?*Ym")
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"=r ,o ,*y,m*y,*y,*x,m ,*x,*x,*x,m ,*x,*x,?*x,?*Ym")
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(match_operand:DI 1 "general_operand"
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"riFo,riF,C ,*y ,m ,C ,*Y2,*Y2,m ,C ,*x,*x,m ,*Ym ,*Y2"))]
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"riFo,riF,C ,*y ,m ,C ,*x,*x,m ,C ,*x,*x,m ,*Ym,*x"))]
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"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
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{
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switch (get_attr_type (insn))
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@ -2198,9 +2205,12 @@
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}
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}
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[(set (attr "isa")
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(if_then_else (eq_attr "alternative" "9,10,11,12")
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(const_string "noavx")
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(const_string "*")))
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(cond [(eq_attr "alternative" "5,6,7,8,13,14")
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(const_string "sse2")
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(eq_attr "alternative" "9,10,11,12")
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(const_string "noavx")
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]
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(const_string "*")))
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(set (attr "type")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "multi")
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@ -2770,7 +2780,7 @@
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(define_insn "*pushdf_rex64"
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[(set (match_operand:DF 0 "push_operand" "=<,<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFm,Y2"))]
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(match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFm,x"))]
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"TARGET_64BIT"
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{
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/* This insn should be already split before reg-stack. */
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@ -2786,13 +2796,14 @@
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(define_insn "*pushdf"
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[(set (match_operand:DF 0 "push_operand" "=<,<,<")
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(match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFo,Y2"))]
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(match_operand:DF 1 "general_no_elim_operand" "f,Yd*rFo,x"))]
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"!TARGET_64BIT"
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{
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/* This insn should be already split before reg-stack. */
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gcc_unreachable ();
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}
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[(set_attr "type" "multi")
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[(set_attr "isa" "*,*,sse2")
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(set_attr "type" "multi")
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(set_attr "unit" "i387,*,*")
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(set_attr "mode" "DF,DI,DF")])
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@ -2976,9 +2987,9 @@
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(define_insn "*movdf_internal_rex64"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f,m,f,?r,?m,?r,!o,Y2*x,Y2*x,Y2*x,m ,Yi,r ")
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"=f,m,f,?r,?m,?r,!o,x,x,x,m,Yi,r ")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,rm,r ,F ,F ,C ,Y2*x,m ,Y2*x,r ,Yi"))]
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"fm,f,G,rm,r ,F ,F ,C,x,m,x,r ,Yi"))]
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"TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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@ -3112,9 +3123,9 @@
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;; Possible store forwarding (partial memory) stall in alternative 4.
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(define_insn "*movdf_internal"
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[(set (match_operand:DF 0 "nonimmediate_operand"
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"=f,m,f,?Yd*r ,!o ,Y2*x,Y2*x,Y2*x,m ")
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"=f,m,f,?Yd*r ,!o ,x,x,x,m,*x,*x,*x,m")
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(match_operand:DF 1 "general_operand"
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"fm,f,G,Yd*roF,FYd*r,C ,Y2*x,m ,Y2*x"))]
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"fm,f,G,Yd*roF,FYd*r,C,x,m,x,C ,*x,m ,*x"))]
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"!TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (!can_create_pseudo_p ()
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|| (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
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@ -3142,11 +3153,15 @@
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return "#";
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case 5:
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case 9:
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return standard_sse_constant_opcode (insn, operands[1]);
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case 6:
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case 7:
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case 8:
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case 10:
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case 11:
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case 12:
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switch (get_attr_mode (insn))
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{
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case MODE_V2DF:
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@ -3173,7 +3188,11 @@
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gcc_unreachable ();
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}
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}
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[(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
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[(set (attr "isa")
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(if_then_else (eq_attr "alternative" "5,6,7,8")
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(const_string "sse2")
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(const_string "*")))
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(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov")
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(set (attr "prefix")
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(if_then_else (eq_attr "alternative" "0,1,2,3,4")
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(const_string "orig")
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@ -3191,12 +3210,12 @@
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/* For SSE1, we have many fewer alternatives. */
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(eq (symbol_ref "TARGET_SSE2") (const_int 0))
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(if_then_else
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(eq_attr "alternative" "5,6")
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(eq_attr "alternative" "5,6,9,10")
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(const_string "V4SF")
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(const_string "V2SF"))
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/* xorps is one byte shorter. */
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(eq_attr "alternative" "5")
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(eq_attr "alternative" "5,9")
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(cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
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(const_int 0))
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(const_string "V4SF")
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@ -3211,7 +3230,7 @@
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chains, otherwise use short move to avoid extra work.
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movaps encodes one byte shorter. */
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(eq_attr "alternative" "6")
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(eq_attr "alternative" "6,10")
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(cond
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[(ne (symbol_ref "optimize_function_for_size_p (cfun)")
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(const_int 0))
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@ -3224,7 +3243,7 @@
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/* For architectures resolving dependencies on register
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parts we may avoid extra work to zero out upper part
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of register. */
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(eq_attr "alternative" "7")
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(eq_attr "alternative" "7,11")
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(if_then_else
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(ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
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(const_int 0))
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@ -3445,7 +3464,7 @@
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})
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(define_insn "*zero_extendsidi2_rex64"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*Y2")
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,o,?*Ym,?*y,?*Yi,*x")
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(zero_extend:DI
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(match_operand:SI 1 "nonimmediate_operand" "rm,0,r ,m ,r ,m")))]
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"TARGET_64BIT"
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@ -3470,7 +3489,7 @@
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;; %%% Kill me once multi-word ops are sane.
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(define_insn "zero_extendsidi2_1"
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[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*Y2")
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,?r,?o,?*Ym,?*y,?*Yi,*x")
|
||||
(zero_extend:DI
|
||||
(match_operand:SI 1 "nonimmediate_operand" "0,rm,r ,r ,m ,r ,m")))
|
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(clobber (reg:CC FLAGS_REG))]
|
||||
@ -3483,7 +3502,8 @@
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movd\t{%1, %0|%0, %1}
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%vmovd\t{%1, %0|%0, %1}
|
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%vmovd\t{%1, %0|%0, %1}"
|
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[(set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")
|
||||
[(set_attr "isa" "*,*,*,*,*,*,sse2")
|
||||
(set_attr "type" "multi,multi,multi,mmxmov,mmxmov,ssemov,ssemov")
|
||||
(set_attr "prefix" "*,*,*,orig,orig,maybe_vex,maybe_vex")
|
||||
(set_attr "mode" "SI,SI,SI,DI,DI,TI,TI")])
|
||||
|
||||
@ -4115,10 +4135,10 @@
|
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(set_attr "mode" "SF")])
|
||||
|
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(define_insn "*truncdfsf_mixed"
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=m,Y2 ,?f,?x,?*r")
|
||||
[(set (match_operand:SF 0 "nonimmediate_operand" "=m,x ,?f,?x,?*r")
|
||||
(float_truncate:SF
|
||||
(match_operand:DF 1 "nonimmediate_operand" "f ,Y2m,f ,f ,f")))
|
||||
(clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
|
||||
(match_operand:DF 1 "nonimmediate_operand" "f ,xm,f ,f ,f")))
|
||||
(clobber (match_operand:SF 2 "memory_operand" "=X,X ,m ,m ,m"))]
|
||||
"TARGET_MIX_SSE_I387"
|
||||
{
|
||||
switch (which_alternative)
|
||||
@ -4132,7 +4152,8 @@
|
||||
return "#";
|
||||
}
|
||||
}
|
||||
[(set_attr "type" "fmov,ssecvt,multi,multi,multi")
|
||||
[(set_attr "isa" "*,sse2,*,*,*")
|
||||
(set_attr "type" "fmov,ssecvt,multi,multi,multi")
|
||||
(set_attr "unit" "*,*,i387,i387,i387")
|
||||
(set_attr "prefix" "orig,maybe_vex,orig,orig,orig")
|
||||
(set_attr "mode" "SF")])
|
||||
@ -4219,7 +4240,7 @@
|
||||
(set_attr "mode" "SF")])
|
||||
|
||||
(define_insn "*truncxfdf2_mixed"
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?Y2,?*r")
|
||||
[(set (match_operand:DF 0 "nonimmediate_operand" "=m,?f,?x,?*r")
|
||||
(float_truncate:DF
|
||||
(match_operand:XF 1 "register_operand" "f ,f ,f ,f")))
|
||||
(clobber (match_operand:DF 2 "memory_operand" "=X,m ,m ,m"))]
|
||||
@ -4228,7 +4249,8 @@
|
||||
gcc_assert (!which_alternative);
|
||||
return output_387_reg_move (insn, operands);
|
||||
}
|
||||
[(set_attr "type" "fmov,multi,multi,multi")
|
||||
[(set_attr "isa" "*,*,sse2,*")
|
||||
(set_attr "type" "fmov,multi,multi,multi")
|
||||
(set_attr "unit" "*,i387,i387,i387")
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
@ -4453,10 +4475,10 @@
|
||||
|
||||
;; Avoid vector decoded forms of the instruction.
|
||||
(define_peephole2
|
||||
[(match_scratch:DF 2 "Y2")
|
||||
[(match_scratch:DF 2 "x")
|
||||
(set (match_operand:SWI48x 0 "register_operand" "")
|
||||
(fix:SWI48x (match_operand:DF 1 "memory_operand" "")))]
|
||||
"TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
|
||||
"TARGET_SSE2 && TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
|
||||
[(set (match_dup 2) (match_dup 1))
|
||||
(set (match_dup 0) (fix:SWI48x (match_dup 2)))])
|
||||
|
||||
|
||||
@ -66,9 +66,9 @@
|
||||
;; movd instead of movq is required to handle broken assemblers.
|
||||
(define_insn "*mov<mode>_internal_rex64"
|
||||
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
|
||||
"=rm,r,!?y,!y,!?y,m ,!y ,*Y2,x,x ,m,r ,Yi")
|
||||
"=rm,r,!?y,!y,!?y,m ,!y ,*x,x,x ,m,r ,Yi")
|
||||
(match_operand:MMXMODEI8 1 "vector_move_operand"
|
||||
"Cr ,m,C ,!y,m ,!?y,*Y2,!y ,C,xm,x,Yi,r"))]
|
||||
"Cr ,m,C ,!y,m ,!?y,*x,!y ,C,xm,x,Yi,r"))]
|
||||
"TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
@ -113,9 +113,9 @@
|
||||
|
||||
(define_insn "*mov<mode>_internal"
|
||||
[(set (match_operand:MMXMODEI8 0 "nonimmediate_operand"
|
||||
"=!?y,!y,!?y,m ,!y ,*Y2,*Y2,*Y2 ,m ,*x,*x,*x,m ,r ,m")
|
||||
"=!?y,!y,!?y,m ,!y,*x,*x,*x ,m ,*x,*x,*x,m ,r ,m")
|
||||
(match_operand:MMXMODEI8 1 "vector_move_operand"
|
||||
"C ,!y,m ,!?y,*Y2,!y ,C ,*Y2m,*Y2,C ,*x,m ,*x,irm,r"))]
|
||||
"C ,!y,m ,!?y,*x,!y,C ,*xm,*x,C ,*x,m ,*x,irm,r"))]
|
||||
"!TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
@ -135,9 +135,12 @@
|
||||
#
|
||||
#"
|
||||
[(set (attr "isa")
|
||||
(if_then_else (eq_attr "alternative" "9,10,11,12")
|
||||
(const_string "noavx")
|
||||
(const_string "*")))
|
||||
(cond [(eq_attr "alternative" "4,5,6,7,8")
|
||||
(const_string "sse2")
|
||||
(eq_attr "alternative" "9,10,11,12")
|
||||
(const_string "noavx")
|
||||
]
|
||||
(const_string "*")))
|
||||
(set (attr "type")
|
||||
(cond [(eq_attr "alternative" "0")
|
||||
(const_string "mmx")
|
||||
@ -183,9 +186,9 @@
|
||||
;; movd instead of movq is required to handle broken assemblers.
|
||||
(define_insn "*movv2sf_internal_rex64"
|
||||
[(set (match_operand:V2SF 0 "nonimmediate_operand"
|
||||
"=rm,r,!?y,!y,!?y,m ,!y ,*Y2,x,x,x,m,r ,Yi")
|
||||
"=rm,r,!?y,!y,!?y,m ,!y,*x,x,x,x,m,r ,Yi")
|
||||
(match_operand:V2SF 1 "vector_move_operand"
|
||||
"Cr ,m,C ,!y,m ,!?y,*Y2,!y ,C,x,m,x,Yi,r"))]
|
||||
"Cr ,m,C ,!y,m ,!?y,*x,!y,C,x,m,x,Yi,r"))]
|
||||
"TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
@ -232,9 +235,9 @@
|
||||
|
||||
(define_insn "*movv2sf_internal"
|
||||
[(set (match_operand:V2SF 0 "nonimmediate_operand"
|
||||
"=!?y,!y,!?y,m ,!y ,*Y2,*x,*x,*x,m ,r ,m")
|
||||
"=!?y,!y,!?y,m ,!y,*x,*x,*x,*x,m ,r ,m")
|
||||
(match_operand:V2SF 1 "vector_move_operand"
|
||||
"C ,!y,m ,!?y,*Y2,!y ,C ,*x,m ,*x,irm,r"))]
|
||||
"C ,!y,m ,!?y,*x,!y,C ,*x,m ,*x,irm,r"))]
|
||||
"!TARGET_64BIT && TARGET_MMX
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
@ -250,7 +253,11 @@
|
||||
%vmovlps\t{%1, %0|%0, %1}
|
||||
#
|
||||
#"
|
||||
[(set (attr "type")
|
||||
[(set (attr "isa")
|
||||
(if_then_else (eq_attr "alternative" "4,5")
|
||||
(const_string "sse2")
|
||||
(const_string "*")))
|
||||
(set (attr "type")
|
||||
(cond [(eq_attr "alternative" "0")
|
||||
(const_string "mmx")
|
||||
(eq_attr "alternative" "1,2,3")
|
||||
@ -1388,9 +1395,9 @@
|
||||
;; Avoid combining registers from different units in a single alternative,
|
||||
;; see comment above inline_secondary_memory_needed function in i386.c
|
||||
(define_insn "*vec_extractv2si_1"
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=y,Y2,Y2,x,y,x,r")
|
||||
[(set (match_operand:SI 0 "nonimmediate_operand" "=y,x,x,x,y,x,r")
|
||||
(vec_select:SI
|
||||
(match_operand:V2SI 1 "nonimmediate_operand" " 0,0 ,Y2,0,o,o,o")
|
||||
(match_operand:V2SI 1 "nonimmediate_operand" " 0,0,x,0,o,o,o")
|
||||
(parallel [(const_int 1)])))]
|
||||
"TARGET_MMX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
"@
|
||||
@ -1401,7 +1408,11 @@
|
||||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
|
||||
[(set (attr "isa")
|
||||
(if_then_else (eq_attr "alternative" "1,2")
|
||||
(const_string "sse2")
|
||||
(const_string "*")))
|
||||
(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
|
||||
(set_attr "length_immediate" "*,*,1,*,*,*,*")
|
||||
(set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
|
||||
|
||||
|
||||
@ -3534,13 +3534,13 @@
|
||||
;; see comment above inline_secondary_memory_needed function in i386.c
|
||||
(define_insn "vec_set<mode>_0"
|
||||
[(set (match_operand:VI4F_128 0 "nonimmediate_operand"
|
||||
"=Y4,Y2,Y2,x,x,x,Y4 ,x ,m,m ,m")
|
||||
"=x,x,x ,x,x,x,x ,x ,m,m ,m")
|
||||
(vec_merge:VI4F_128
|
||||
(vec_duplicate:VI4F_128
|
||||
(match_operand:<ssescalarmode> 2 "general_operand"
|
||||
" Y4,m ,*r,m,x,x,*rm,*rm,x,fF,*r"))
|
||||
" x,m,*r,m,x,x,*rm,*rm,x,fF,*r"))
|
||||
(match_operand:VI4F_128 1 "vector_move_operand"
|
||||
" C ,C ,C ,C,0,x,0 ,x ,0,0 ,0")
|
||||
" C,C,C ,C,0,x,0 ,x ,0,0 ,0")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
@ -3555,7 +3555,7 @@
|
||||
#
|
||||
#
|
||||
#"
|
||||
[(set_attr "isa" "*,*,*,noavx,noavx,avx,noavx,avx,*,*,*")
|
||||
[(set_attr "isa" "sse4,sse2,sse2,noavx,noavx,avx,sse4_noavx,avx,*,*,*")
|
||||
(set (attr "type")
|
||||
(cond [(eq_attr "alternative" "0,6,7")
|
||||
(const_string "sselog")
|
||||
@ -3969,11 +3969,11 @@
|
||||
})
|
||||
|
||||
(define_insn "*vec_interleave_highv2df"
|
||||
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,m")
|
||||
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m")
|
||||
(vec_select:V2DF
|
||||
(vec_concat:V4DF
|
||||
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,o ,o,o,x")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,0,x,0"))
|
||||
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,o,o,o,x")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1,0,x,0"))
|
||||
(parallel [(const_int 1)
|
||||
(const_int 3)])))]
|
||||
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 1)"
|
||||
@ -3984,7 +3984,7 @@
|
||||
movlpd\t{%H1, %0|%0, %H1}
|
||||
vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
|
||||
%vmovhpd\t{%1, %0|%0, %1}"
|
||||
[(set_attr "isa" "noavx,avx,*,noavx,avx,*")
|
||||
[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")
|
||||
(set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
|
||||
(set_attr "prefix_data16" "*,*,*,1,*,1")
|
||||
(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
|
||||
@ -4071,11 +4071,11 @@
|
||||
})
|
||||
|
||||
(define_insn "*vec_interleave_lowv2df"
|
||||
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,Y3,x,x,o")
|
||||
[(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,o")
|
||||
(vec_select:V2DF
|
||||
(vec_concat:V4DF
|
||||
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,m ,0,x,0")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1 ,m,m,x"))
|
||||
(match_operand:V2DF 1 "nonimmediate_operand" " 0,x,m,0,x,0")
|
||||
(match_operand:V2DF 2 "nonimmediate_operand" " x,x,1,m,m,x"))
|
||||
(parallel [(const_int 0)
|
||||
(const_int 2)])))]
|
||||
"TARGET_SSE2 && ix86_vec_interleave_v2df_operator_ok (operands, 0)"
|
||||
@ -4086,7 +4086,7 @@
|
||||
movhpd\t{%2, %0|%0, %2}
|
||||
vmovhpd\t{%2, %1, %0|%0, %1, %2}
|
||||
%vmovlpd\t{%2, %H0|%H0, %2}"
|
||||
[(set_attr "isa" "noavx,avx,*,noavx,avx,*")
|
||||
[(set_attr "isa" "noavx,avx,sse3,noavx,avx,*")
|
||||
(set_attr "type" "sselog,sselog,sselog,ssemov,ssemov,ssemov")
|
||||
(set_attr "prefix_data16" "*,*,*,1,*,1")
|
||||
(set_attr "prefix" "orig,vex,maybe_vex,orig,vex,maybe_vex")
|
||||
@ -4606,10 +4606,10 @@
|
||||
(set_attr "mode" "DF")])
|
||||
|
||||
(define_insn "*vec_concatv2df"
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=Y2,x,Y2,x,Y2,x,x")
|
||||
[(set (match_operand:V2DF 0 "register_operand" "=x,x,x,x,x,x,x")
|
||||
(vec_concat:V2DF
|
||||
(match_operand:DF 1 "nonimmediate_operand" " 0 ,x,0 ,x,m ,0,0")
|
||||
(match_operand:DF 2 "vector_move_operand" " Y2,x,m ,m,C ,x,m")))]
|
||||
(match_operand:DF 1 "nonimmediate_operand" " 0,x,0,x,m,0,0")
|
||||
(match_operand:DF 2 "vector_move_operand" " x,x,m,m,C,x,m")))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
unpcklpd\t{%2, %0|%0, %2}
|
||||
@ -4619,7 +4619,7 @@
|
||||
%vmovsd\t{%1, %0|%0, %1}
|
||||
movlhps\t{%2, %0|%0, %2}
|
||||
movhps\t{%2, %0|%0, %2}"
|
||||
[(set_attr "isa" "noavx,avx,noavx,avx,*,noavx,noavx")
|
||||
[(set_attr "isa" "sse2_noavx,avx,sse2_noavx,avx,sse2,noavx,noavx")
|
||||
(set (attr "type")
|
||||
(if_then_else
|
||||
(eq_attr "alternative" "0,1")
|
||||
@ -7123,11 +7123,11 @@
|
||||
"operands[2] = CONST0_RTX (V4SImode);")
|
||||
|
||||
(define_insn "sse2_loadld"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x,x")
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x,Yi,x,x,x")
|
||||
(vec_merge:V4SI
|
||||
(vec_duplicate:V4SI
|
||||
(match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x,x"))
|
||||
(match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,x")
|
||||
(match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x,x"))
|
||||
(match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0,x")
|
||||
(const_int 1)))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
@ -7136,7 +7136,7 @@
|
||||
movss\t{%2, %0|%0, %2}
|
||||
movss\t{%2, %0|%0, %2}
|
||||
vmovss\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "*,*,noavx,noavx,avx")
|
||||
[(set_attr "isa" "sse2,*,noavx,noavx,avx")
|
||||
(set_attr "type" "ssemov")
|
||||
(set_attr "prefix" "maybe_vex,maybe_vex,orig,orig,vex")
|
||||
(set_attr "mode" "TI,TI,V4SF,SF,SF")])
|
||||
@ -7232,9 +7232,9 @@
|
||||
(set_attr "mode" "V2SF,TI,TI,TI,DI")])
|
||||
|
||||
(define_insn "*vec_extractv2di_1"
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,Y2,Y2,Y2,x,x")
|
||||
[(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,x")
|
||||
(vec_select:DI
|
||||
(match_operand:V2DI 1 "nonimmediate_operand" " x,0 ,Y2,o ,x,o")
|
||||
(match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o")
|
||||
(parallel [(const_int 1)])))]
|
||||
"!TARGET_64BIT && TARGET_SSE
|
||||
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
|
||||
@ -7245,7 +7245,7 @@
|
||||
%vmovq\t{%H1, %0|%0, %H1}
|
||||
movhlps\t{%1, %0|%0, %1}
|
||||
movlps\t{%H1, %0|%0, %H1}"
|
||||
[(set_attr "isa" "*,noavx,avx,*,noavx,noavx")
|
||||
[(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx")
|
||||
(set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov")
|
||||
(set_attr "length_immediate" "*,1,1,*,*,*")
|
||||
(set_attr "memory" "*,none,none,*,*,*")
|
||||
@ -7267,14 +7267,15 @@
|
||||
(set_attr "mode" "TI,V4SF")])
|
||||
|
||||
(define_insn "*vec_dupv4si"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=Y2,x")
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x,x")
|
||||
(vec_duplicate:V4SI
|
||||
(match_operand:SI 1 "register_operand" " Y2,0")))]
|
||||
(match_operand:SI 1 "register_operand" " x,0")))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
pshufd\t{$0, %1, %0|%0, %1, 0}
|
||||
shufps\t{$0, %0, %0|%0, %0, 0}"
|
||||
[(set_attr "type" "sselog1")
|
||||
[(set_attr "isa" "sse2,*")
|
||||
(set_attr "type" "sselog1")
|
||||
(set_attr "length_immediate" "1")
|
||||
(set_attr "mode" "TI,V4SF")])
|
||||
|
||||
@ -7293,14 +7294,15 @@
|
||||
(set_attr "mode" "TI,TI,DF")])
|
||||
|
||||
(define_insn "*vec_dupv2di"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x,x")
|
||||
(vec_duplicate:V2DI
|
||||
(match_operand:DI 1 "register_operand" " 0 ,0")))]
|
||||
(match_operand:DI 1 "register_operand" " 0,0")))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
punpcklqdq\t%0, %0
|
||||
movlhps\t%0, %0"
|
||||
[(set_attr "type" "sselog1,ssemov")
|
||||
[(set_attr "isa" "sse2,*")
|
||||
(set_attr "type" "sselog1,ssemov")
|
||||
(set_attr "mode" "TI,V4SF")])
|
||||
|
||||
(define_insn "*vec_concatv2si_sse4_1"
|
||||
@ -7356,10 +7358,10 @@
|
||||
(set_attr "mode" "V4SF,V4SF,DI,DI")])
|
||||
|
||||
(define_insn "*vec_concatv4si"
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x,x,x")
|
||||
[(set (match_operand:V4SI 0 "register_operand" "=x,x,x,x,x")
|
||||
(vec_concat:V4SI
|
||||
(match_operand:V2SI 1 "register_operand" " 0 ,x,0,0,x")
|
||||
(match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,x,m,m")))]
|
||||
(match_operand:V2SI 1 "register_operand" " 0,x,0,0,x")
|
||||
(match_operand:V2SI 2 "nonimmediate_operand" " x,x,x,m,m")))]
|
||||
"TARGET_SSE"
|
||||
"@
|
||||
punpcklqdq\t{%2, %0|%0, %2}
|
||||
@ -7367,7 +7369,7 @@
|
||||
movlhps\t{%2, %0|%0, %2}
|
||||
movhps\t{%2, %0|%0, %2}
|
||||
vmovhps\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx,noavx,noavx,avx")
|
||||
[(set_attr "isa" "sse2_noavx,avx,noavx,noavx,avx")
|
||||
(set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov")
|
||||
(set_attr "prefix" "orig,vex,orig,orig,vex")
|
||||
(set_attr "mode" "TI,TI,V4SF,V2SF,V2SF")])
|
||||
@ -7375,12 +7377,12 @@
|
||||
;; movd instead of movq is required to handle broken assemblers.
|
||||
(define_insn "*vec_concatv2di_rex64"
|
||||
[(set (match_operand:V2DI 0 "register_operand"
|
||||
"=Y4,x ,x ,Yi,!x,x,x,x,x")
|
||||
"=x,x ,x ,Yi,!x,x,x,x,x")
|
||||
(vec_concat:V2DI
|
||||
(match_operand:DI 1 "nonimmediate_operand"
|
||||
" 0 ,x ,xm,r ,*y,0,x,0,x")
|
||||
" 0,x ,xm,r ,*y,0,x,0,x")
|
||||
(match_operand:DI 2 "vector_move_operand"
|
||||
" rm,rm,C ,C ,C ,x,x,m,m")))]
|
||||
"rm,rm,C ,C ,C ,x,x,m,m")))]
|
||||
"TARGET_64BIT"
|
||||
"@
|
||||
pinsrq\t{$1, %2, %0|%0, %2, 1}
|
||||
@ -7392,7 +7394,7 @@
|
||||
vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
|
||||
movhps\t{%2, %0|%0, %2}
|
||||
vmovhps\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "noavx,avx,*,*,*,noavx,avx,noavx,avx")
|
||||
[(set_attr "isa" "sse4_noavx,avx,*,*,*,noavx,avx,noavx,avx")
|
||||
(set (attr "type")
|
||||
(if_then_else
|
||||
(eq_attr "alternative" "0,1,5,6")
|
||||
@ -7410,10 +7412,10 @@
|
||||
(set_attr "mode" "TI,TI,TI,TI,TI,TI,TI,V2SF,V2SF")])
|
||||
|
||||
(define_insn "vec_concatv2di"
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=Y2,?Y2,Y2,x,x,x,x")
|
||||
[(set (match_operand:V2DI 0 "register_operand" "=x,?x,x,x,x,x,x")
|
||||
(vec_concat:V2DI
|
||||
(match_operand:DI 1 "nonimmediate_operand" "Y2m,*y , 0,x,0,0,x")
|
||||
(match_operand:DI 2 "vector_move_operand" " C , C ,Y2,x,x,m,m")))]
|
||||
(match_operand:DI 1 "nonimmediate_operand" "xm,*y,0,x,0,0,x")
|
||||
(match_operand:DI 2 "vector_move_operand" " C, C,x,x,x,m,m")))]
|
||||
"!TARGET_64BIT && TARGET_SSE"
|
||||
"@
|
||||
%vmovq\t{%1, %0|%0, %1}
|
||||
@ -7423,7 +7425,7 @@
|
||||
movlhps\t{%2, %0|%0, %2}
|
||||
movhps\t{%2, %0|%0, %2}
|
||||
vmovhps\t{%2, %1, %0|%0, %1, %2}"
|
||||
[(set_attr "isa" "*,*,noavx,avx,noavx,noavx,avx")
|
||||
[(set_attr "isa" "sse2,sse2,sse2_noavx,avx,noavx,noavx,avx")
|
||||
(set_attr "type" "ssemov,ssemov,sselog,sselog,ssemov,ssemov,ssemov")
|
||||
(set_attr "prefix" "maybe_vex,orig,orig,vex,orig,orig,vex")
|
||||
(set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF,V2SF")])
|
||||
|
||||
Loading…
Reference in New Issue
Block a user