re PR target/52199 (V2DI vec_duplicate ICE on valid code)
[gcc] 2012-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/52199 * config/rs6000/rs6000.c (rs6000_expand_vector_init): Use force_reg instead of copy_to_reg for better optimization. Force non-register or memory operands into a register. [gcc/testsuite] 2012-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/52199 * gcc.target/powerpc/pr52199.c: New file. From-SVN: r184287
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@ -1,3 +1,10 @@
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2012-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/52199
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* config/rs6000/rs6000.c (rs6000_expand_vector_init): Use
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force_reg instead of copy_to_reg for better optimization. Force
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non-register or memory operands into a register.
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2012-02-15 Andrew MacLeod <amacleod@redhat.com>
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* extend.texi: Reserve upper bits of memory model for future use.
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@ -4701,28 +4701,25 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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/* Double word values on VSX can use xxpermdi or lxvdsx. */
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if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
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{
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rtx op0 = XVECEXP (vals, 0, 0);
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rtx op1 = XVECEXP (vals, 0, 1);
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if (all_same)
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{
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rtx element = XVECEXP (vals, 0, 0);
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if (!MEM_P (op0) && !REG_P (op0))
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op0 = force_reg (inner_mode, op0);
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if (mode == V2DFmode)
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emit_insn (gen_vsx_splat_v2df (target, element));
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emit_insn (gen_vsx_splat_v2df (target, op0));
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else
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emit_insn (gen_vsx_splat_v2di (target, element));
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emit_insn (gen_vsx_splat_v2di (target, op0));
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}
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else
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{
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op0 = force_reg (inner_mode, op0);
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op1 = force_reg (inner_mode, op1);
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if (mode == V2DFmode)
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{
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rtx op0 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 0));
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rtx op1 = copy_to_mode_reg (DFmode, XVECEXP (vals, 0, 1));
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emit_insn (gen_vsx_concat_v2df (target, op0, op1));
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}
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emit_insn (gen_vsx_concat_v2df (target, op0, op1));
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else
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{
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rtx op0 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 0));
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rtx op1 = copy_to_mode_reg (DImode, XVECEXP (vals, 0, 1));
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emit_insn (gen_vsx_concat_v2di (target, op0, op1));
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}
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emit_insn (gen_vsx_concat_v2di (target, op0, op1));
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}
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return;
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}
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@ -4736,7 +4733,7 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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if (all_same)
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{
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rtx freg = gen_reg_rtx (V4SFmode);
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rtx sreg = copy_to_reg (XVECEXP (vals, 0, 0));
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rtx sreg = force_reg (SFmode, XVECEXP (vals, 0, 0));
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emit_insn (gen_vsx_xscvdpsp_scalar (freg, sreg));
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emit_insn (gen_vsx_xxspltw_v4sf (target, freg, const0_rtx));
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@ -4747,13 +4744,13 @@ rs6000_expand_vector_init (rtx target, rtx vals)
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rtx dbl_odd = gen_reg_rtx (V2DFmode);
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rtx flt_even = gen_reg_rtx (V4SFmode);
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rtx flt_odd = gen_reg_rtx (V4SFmode);
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rtx op0 = force_reg (SFmode, XVECEXP (vals, 0, 0));
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rtx op1 = force_reg (SFmode, XVECEXP (vals, 0, 1));
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rtx op2 = force_reg (SFmode, XVECEXP (vals, 0, 2));
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rtx op3 = force_reg (SFmode, XVECEXP (vals, 0, 3));
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emit_insn (gen_vsx_concat_v2sf (dbl_even,
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copy_to_reg (XVECEXP (vals, 0, 0)),
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copy_to_reg (XVECEXP (vals, 0, 1))));
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emit_insn (gen_vsx_concat_v2sf (dbl_odd,
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copy_to_reg (XVECEXP (vals, 0, 2)),
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copy_to_reg (XVECEXP (vals, 0, 3))));
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emit_insn (gen_vsx_concat_v2sf (dbl_even, op0, op1));
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emit_insn (gen_vsx_concat_v2sf (dbl_odd, op2, op3));
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emit_insn (gen_vsx_xvcvdpsp (flt_even, dbl_even));
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emit_insn (gen_vsx_xvcvdpsp (flt_odd, dbl_odd));
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rs6000_expand_extract_even (target, flt_even, flt_odd);
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@ -1,3 +1,8 @@
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2012-02-15 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/52199
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* gcc.target/powerpc/pr52199.c: New file.
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2012-02-15 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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PR target/52152
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24
gcc/testsuite/gcc.target/powerpc/pr52199.c
Normal file
24
gcc/testsuite/gcc.target/powerpc/pr52199.c
Normal file
@ -0,0 +1,24 @@
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/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
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/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
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/* { dg-require-effective-target powerpc_vsx_ok } */
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/* { dg-options "-O3 -mcpu=power7 -fmerge-all-constants" } */
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struct locale_time_t
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{
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const char *abday[7];
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const unsigned int *wabday[7];
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};
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static const unsigned int empty_wstr[1] = { 0 };
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void
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time_read (struct locale_time_t *time)
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{
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int cnt;
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for (cnt=0; cnt < 7; cnt++)
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{
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time->abday[cnt] = "";
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time->wabday[cnt] = empty_wstr;
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}
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}
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