bfin.md (sp_or_sm, [...]): New macro.
gcc/ * config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro. (ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts, ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3, ssaddhi3_parts and sssubhi3_parts. (flag_mulhi3_parts): Produce a HImode output rather than trying to set a VEC_SELECT. * config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU): Adjust accordingly. gcc/testsuite/ * gcc.target/bfin/20090411-1.c: New test. From-SVN: r146929
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
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commit
a0a31d1ec3
@ -1,3 +1,14 @@
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2009-04-29 Bernd Schmidt <bernd.schmidt@analog.com>
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* config/bfin/bfin.md (sp_or_sm, spm_string, spm_name): New macro.
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(ss<spm_name>hi3, ss<spm_name>hi3_parts, ss<spm_name>hi3_low_parts,
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ss<spm_name_hi3_high_parts): New patterns, replacing ssaddhi3, ssubhi3,
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ssaddhi3_parts and sssubhi3_parts.
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(flag_mulhi3_parts): Produce a HImode output rather than trying to set
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a VEC_SELECT.
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* config/bfin/bfin.c (bfin_expand_builtin, case BFIN_BUILTIN_CPLX_SQU):
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Adjust accordingly.
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2009-04-28 Richard Guenther <rguenther@suse.de>
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* tree-vect-loop.c (get_initial_def_for_induction): Use
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@ -6169,15 +6169,14 @@ bfin_expand_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
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emit_insn (gen_flag_mulv2hi (tmp1, op0, op0, GEN_INT (MACFLAG_NONE)));
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emit_insn (gen_flag_mulhi_parts (tmp2, op0, op0, const0_rtx,
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emit_insn (gen_flag_mulhi_parts (gen_lowpart (HImode, tmp2), op0, op0,
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const0_rtx, const1_rtx,
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GEN_INT (MACFLAG_NONE)));
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emit_insn (gen_ssaddhi3_parts (target, tmp2, tmp2, const1_rtx,
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const0_rtx, const0_rtx));
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emit_insn (gen_sssubhi3_parts (target, tmp1, tmp1, const0_rtx,
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const0_rtx, const1_rtx));
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emit_insn (gen_ssaddhi3_high_parts (target, tmp2, tmp2, tmp2, const0_rtx,
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const0_rtx));
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emit_insn (gen_sssubhi3_low_parts (target, target, tmp1, tmp1,
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const0_rtx, const1_rtx));
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return target;
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@ -2962,74 +2962,82 @@
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;; Unusual arithmetic operations on 16-bit registers.
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(define_insn "ssaddhi3"
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(define_code_iterator sp_or_sm [ss_plus ss_minus])
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(define_code_attr spm_string [(ss_plus "+") (ss_minus "-")])
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(define_code_attr spm_name [(ss_plus "add") (ss_minus "sub")])
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(define_insn "ss<spm_name>hi3"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(ss_plus:HI (match_operand:HI 1 "register_operand" "d")
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(sp_or_sm:HI (match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")))]
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""
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"%h0 = %h1 + %h2 (S)%!"
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"%h0 = %h1 <spm_string> %h2 (S)%!"
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[(set_attr "type" "dsp32")])
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(define_insn "ssaddhi3_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(ss_plus:HI (vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
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""
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{
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const char *templates[] = {
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"%h0 = %h1 + %h2 (S)%!",
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"%d0 = %h1 + %h2 (S)%!",
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"%h0 = %d1 + %h2 (S)%!",
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"%d0 = %d1 + %h2 (S)%!",
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"%h0 = %h1 + %d2 (S)%!",
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"%d0 = %h1 + %d2 (S)%!",
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"%h0 = %d1 + %d2 (S)%!",
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"%d0 = %d1 + %d2 (S)%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
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+ (INTVAL (operands[5]) << 2);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "sssubhi3_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(ss_minus:HI (vec_select:HI
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(define_insn "ss<spm_name>hi3_parts"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(sp_or_sm:HI (vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")]))))]
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""
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))))]
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""
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{
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const char *templates[] = {
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"%h0 = %h1 - %h2 (S)%!",
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"%d0 = %h1 - %h2 (S)%!",
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"%h0 = %d1 - %h2 (S)%!",
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"%d0 = %d1 - %h2 (S)%!",
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"%h0 = %h1 - %d2 (S)%!",
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"%d0 = %h1 - %d2 (S)%!",
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"%h0 = %d1 - %d2 (S)%!",
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"%d0 = %d1 - %d2 (S)%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
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+ (INTVAL (operands[5]) << 2);
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"%h0 = %h1 <spm_string> %h2 (S)%!",
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"%h0 = %d1 <spm_string> %h2 (S)%!",
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"%h0 = %h1 <spm_string> %d2 (S)%!",
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"%h0 = %d1 <spm_string> %d2 (S)%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "sssubhi3"
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[(set (match_operand:HI 0 "register_operand" "=d")
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(ss_minus:HI (match_operand:HI 1 "register_operand" "d")
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(match_operand:HI 2 "register_operand" "d")))]
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""
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"%h0 = %h1 - %h2 (S)%!"
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(define_insn "ss<spm_name>hi3_low_parts"
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(vec_concat:V2HI
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
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(parallel [(const_int 0)]))
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(sp_or_sm:HI (vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 3 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")])))))]
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""
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{
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const char *templates[] = {
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"%h0 = %h2 <spm_string> %h3 (S)%!",
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"%h0 = %d2 <spm_string> %h3 (S)%!",
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"%h0 = %h2 <spm_string> %d3 (S)%!",
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"%h0 = %d2 <spm_string> %d3 (S)%!" };
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int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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(define_insn "ss<spm_name>hi3_high_parts"
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[(set (match_operand:V2HI 0 "register_operand" "=d")
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(vec_concat:V2HI
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(sp_or_sm:HI (vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 3 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")])))
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(vec_select:HI (match_operand:V2HI 1 "register_operand" "0")
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(parallel [(const_int 1)]))))]
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""
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{
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const char *templates[] = {
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"%d0 = %h2 <spm_string> %h3 (S)%!",
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"%d0 = %d2 <spm_string> %h3 (S)%!",
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"%d0 = %h2 <spm_string> %d3 (S)%!",
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"%d0 = %d2 <spm_string> %d3 (S)%!" };
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int alt = INTVAL (operands[4]) + (INTVAL (operands[5]) << 1);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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;; V2HI vector insns
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@ -3239,30 +3247,23 @@
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[(set_attr "type" "dsp32")])
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(define_insn "flag_mulhi_parts"
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[(set (vec_select:HI
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(match_operand:V2HI 0 "register_operand" "d")
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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[(set (match_operand:HI 0 "register_operand" "=d")
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(unspec:HI [(vec_select:HI
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(match_operand:V2HI 1 "register_operand" "d")
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(parallel [(match_operand 3 "const01_operand" "P0P1")]))
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(vec_select:HI
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(match_operand:V2HI 2 "register_operand" "d")
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(parallel [(match_operand 5 "const01_operand" "P0P1")]))
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(match_operand 6 "const_int_operand" "n")]
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(parallel [(match_operand 4 "const01_operand" "P0P1")]))
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(match_operand 5 "const_int_operand" "n")]
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UNSPEC_MUL_WITH_FLAG))]
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""
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{
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const char *templates[] = {
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"%h0 = %h1 * %h2 %M6%!",
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"%d0 = %h1 * %h2 %M6%!",
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"%h0 = %d1 * %h2 %M6%!",
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"%d0 = %d1 * %h2 %M6%!",
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"%h0 = %h1 * %d2 %M6%!",
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"%d0 = %h1 * %d2 %M6%!",
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"%h0 = %d1 * %d2 %M6%!",
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"%d0 = %d1 * %d2 %M6%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1)
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+ (INTVAL (operands[5]) << 2);
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"%h0 = %h1 * %h2 %M5%!",
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"%h0 = %d1 * %h2 %M5%!",
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"%h0 = %h1 * %d2 %M5%!",
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"%h0 = %d1 * %d2 %M5%!" };
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int alt = INTVAL (operands[3]) + (INTVAL (operands[4]) << 1);
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return templates[alt];
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}
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[(set_attr "type" "dsp32")])
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@ -1,3 +1,7 @@
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2009-04-29 Bernd Schmidt <bernd.schmidt@analog.com>
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* gcc.target/bfin/20090411-1.c: New test.
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2009-04-29 Anmol P. Paralkar <anmol@freescale.com>
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PR target/39565
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29
gcc/testsuite/gcc.target/bfin/20090411-1.c
Normal file
29
gcc/testsuite/gcc.target/bfin/20090411-1.c
Normal file
@ -0,0 +1,29 @@
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/* { dg-do compile { target bfin-*-* } } */
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/* { dg-options "-O2" } */
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typedef short __v2hi __attribute__ ((vector_size (4)));
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typedef __v2hi raw2x16;
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typedef raw2x16 fract2x16;
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typedef short fract16;
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typedef struct complex_fract16
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{
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fract16 re;
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fract16 im;
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} __attribute__ ((aligned (4))) complex_fract16;
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__inline__ __attribute__ ((always_inline))
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static complex_fract16 csqu_fr16 (complex_fract16 _a)
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{
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complex_fract16 _x;
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fract2x16 i =
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__builtin_bfin_csqu_fr16 (__builtin_bfin_compose_2x16 ((_a).im, (_a).re));
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(_x).re = __builtin_bfin_extract_lo (i);
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(_x).im = __builtin_bfin_extract_hi (i);
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return _x;
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}
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complex_fract16 f (complex_fract16 _a)
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{
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return csqu_fr16 (_a);
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}
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