m68hc11.md ("tstqi_1"): Try to use ldab instead of tst.
* config/m68hc11/m68hc11.md ("tstqi_1"): Try to use ldab instead of tst.
("tstqi" split): Avoid using memory for tstqi on address register.
(splits): Remove constraints.
("cmphi_1_hc12"): New from "cmphi_1" and tuned for 68HC12.
("cmpdf", "cmpsf"): Remove since not used.
("*tbeq", "*tbne", "*tbeq8", "*tbne8"): Also look in cc_status.value2.
(peephole2): New peepholes to optimize tstqi and pre inc/dec addressing.
From-SVN: r50849
This commit is contained in:
Stephane Carrez
Stephane Carrez
parent
015a2e5904
commit
a0df6910e3
@ -1,3 +1,13 @@
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2002-03-15 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* config/m68hc11/m68hc11.md ("tstqi_1"): Try to use ldab instead of tst.
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("tstqi" split): Avoid using memory for tstqi on address register.
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(splits): Remove constraints.
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("cmphi_1_hc12"): New from "cmphi_1" and tuned for 68HC12.
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("cmpdf", "cmpsf"): Remove since not used.
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("*tbeq", "*tbne", "*tbeq8", "*tbne8"): Also look in cc_status.value2.
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(peephole2): New peepholes to optimize tstqi and pre inc/dec addressing.
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2002-03-15 Stephane Carrez <Stephane.Carrez@worldnet.fr>
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* config/m68hc11/m68hc11.md ("negsi2"): Optimize inline case.
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@ -204,27 +204,36 @@
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;;
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;; Split pattern for (tst:QI) on an address register.
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;; The value is saved in memory and we test the low part only.
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;;
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(define_split
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[(set (cc0)
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(match_operand:QI 0 "hard_addr_reg_operand" "xy"))]
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(match_operand:QI 0 "hard_addr_reg_operand" ""))]
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"z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode"
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[(set (match_dup 3) (match_dup 2))
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(set (cc0) (match_dup 4))]
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"operands[2] = gen_rtx (REG, HImode, REGNO (operands[0]));
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operands[3] = gen_rtx (REG, HImode, SOFT_TMP_REGNUM);
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operands[4] = gen_rtx (REG, QImode, SOFT_TMP_REGNUM);")
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[(parallel [(set (reg:HI D_REGNUM) (match_dup 1))
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(set (match_dup 1) (reg:HI D_REGNUM))])
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(set (cc0) (reg:QI D_REGNUM))
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(parallel [(set (reg:HI D_REGNUM) (match_dup 1))
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(set (match_dup 1) (reg:HI D_REGNUM))])]
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"operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]));")
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(define_insn "tstqi_1"
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[(set (cc0)
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(match_operand:QI 0 "tst_operand" "m,d,*A,!u"))]
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""
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"@
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tst\\t%0
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tstb
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#
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tst\\t%b0")
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"*
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{
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if (A_REG_P (operands[0]))
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return \"#\";
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else if (D_REG_P (operands[0]))
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return \"tstb\";
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else if (dead_register_here (insn, d_reg))
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return \"ldab\\t%b0\";
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else
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return \"tst\\t%b0\";
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}")
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;;
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;; tstqi_z_used, cmpqi_z_used and cmphi_z_used are patterns generated
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@ -247,8 +256,8 @@
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(define_split /* "tstqi_z_used" */
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[(set (cc0)
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(match_operand:QI 0 "tst_operand" "m"))
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(use (match_operand:HI 1 "hard_reg_operand" "dxy"))
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(match_operand:QI 0 "tst_operand" ""))
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(use (match_operand:HI 1 "hard_reg_operand" ""))
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(use (reg:HI 11))]
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"z_replacement_completed == 2"
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[(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 1))
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@ -288,8 +297,8 @@
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;;
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(define_split
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[(set (cc0)
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(compare (match_operand:HI 0 "hard_reg_operand" "dxy")
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(match_operand:HI 1 "hard_reg_operand" "Aw")))]
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(compare (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "hard_reg_operand" "")))]
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"reload_completed"
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[(set (match_dup 2) (match_dup 1))
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(set (cc0)
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@ -311,13 +320,33 @@
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DONE;
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}")
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(define_insn "cmphi_1"
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(define_insn "cmphi_1_hc12"
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[(set (cc0)
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(compare (match_operand:HI 0 "tst_operand"
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"x,dy,xyd,?xy,d,m,!u,dxy,dxy")
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"d,?xy,xyd,?xy,d,m,!u,dxy,dxy")
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(match_operand:HI 1 "cmp_operand"
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"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
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""
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"TARGET_M6812"
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"*
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{
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if (H_REG_P (operands[1]) && !H_REG_P (operands[0]))
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{
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cc_status.flags |= CC_REVERSED;
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return \"cp%1\\t%0\";
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}
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else if (H_REG_P (operands[1]))
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return \"#\";
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else
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return \"cp%0\\t%1\";
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}")
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(define_insn "cmphi_1_hc11"
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[(set (cc0)
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(compare (match_operand:HI 0 "tst_operand"
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"dx,y,xyd,?xy,d,m,!u,dxy,dxy")
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(match_operand:HI 1 "cmp_operand"
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"i,i,!u,m,m,dxy,dxy,?*d*A,!*w")))]
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"TARGET_M6811"
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"*
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{
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if (H_REG_P (operands[1]) && !H_REG_P (operands[0]))
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@ -342,9 +371,9 @@
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(define_split /* "cmphi_z_used" */
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[(set (cc0)
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(compare (match_operand:HI 0 "tst_operand" "dxy,m")
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(match_operand:HI 1 "cmp_operand" "m,dxy")))
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(use (match_operand:HI 2 "hard_reg_operand" "dxy,dxy"))
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(compare (match_operand:HI 0 "tst_operand" "")
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(match_operand:HI 1 "cmp_operand" "")))
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(use (match_operand:HI 2 "hard_reg_operand" ""))
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(use (reg:HI 11))]
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"z_replacement_completed == 2"
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[(set (mem:HI (pre_dec:HI (reg:HI SP_REGNUM))) (match_dup 2))
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@ -361,8 +390,8 @@
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;;
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(define_split
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[(set (cc0)
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(compare (match_operand:QI 0 "hard_addr_reg_operand" "xy")
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(match_operand:QI 1 "cmp_operand" "uimA")))]
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(compare (match_operand:QI 0 "hard_addr_reg_operand" "")
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(match_operand:QI 1 "cmp_operand" "")))]
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"z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode"
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[(parallel [(set (reg:HI D_REGNUM) (match_dup 3))
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(set (match_dup 3) (reg:HI D_REGNUM))])
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@ -374,8 +403,8 @@
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(define_split
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[(set (cc0)
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(compare (match_operand:QI 0 "hard_reg_operand" "dxy")
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(match_operand:QI 1 "hard_reg_operand" "dxy")))]
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(compare (match_operand:QI 0 "hard_reg_operand" "")
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(match_operand:QI 1 "hard_reg_operand" "")))]
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"reload_completed"
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[(set (match_dup 3) (match_dup 4))
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(set (cc0)
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@ -413,8 +442,8 @@
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(define_split /* "bitcmpqi" */
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[(set (cc0)
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(and:QI (match_operand:QI 0 "tst_operand" "d")
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(match_operand:QI 1 "hard_addr_reg_operand" "xy")))]
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(and:QI (match_operand:QI 0 "tst_operand" "")
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(match_operand:QI 1 "hard_addr_reg_operand" "")))]
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"z_replacement_completed == 2 && GET_MODE (operands[0]) == QImode"
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[(set (match_dup 3) (match_dup 2))
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(set (cc0) (and:QI (match_dup 0) (match_dup 4)))]
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@ -433,9 +462,9 @@
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(define_split /* "bitcmpqi_z_used" */
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[(set (cc0)
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(and:QI (match_operand:QI 0 "tst_operand" "d,m")
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(match_operand:QI 1 "cmp_operand" "m,d")))
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(use (match_operand:HI 2 "hard_reg_operand" "xy,xy"))
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(and:QI (match_operand:QI 0 "tst_operand" "")
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(match_operand:QI 1 "cmp_operand" "")))
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(use (match_operand:HI 2 "hard_reg_operand" ""))
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(use (reg:HI 11))]
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"z_replacement_completed == 2"
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[(set (mem:HI (pre_dec:HI (reg:HI 3))) (match_dup 2))
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@ -534,30 +563,6 @@
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(set (match_dup 2) (mem:HI (post_inc:HI (reg:HI SP_REGNUM))))]
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"operands[3] = gen_rtx (REG, HImode, SOFT_Z_REGNUM);")
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(define_expand "cmpdf"
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[(set (cc0)
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(compare (match_operand:DF 0 "general_operand" "")
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(match_operand:DF 1 "general_operand" "")))]
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"0"
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"
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{
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m68hc11_compare_op0 = operands[0];
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m68hc11_compare_op1 = operands[1];
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DONE;
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}")
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(define_expand "cmpsf"
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[(set (cc0)
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(compare (match_operand:SF 0 "general_operand" "")
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(match_operand:SF 1 "general_operand" "")))]
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"0"
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"
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{
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m68hc11_compare_op0 = operands[0];
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m68hc11_compare_op1 = operands[1];
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DONE;
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}")
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;;--------------------------------------------------------------------
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;;- Move strict_low_part
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;;--------------------------------------------------------------------
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@ -5909,7 +5914,8 @@
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smaller and a little bit faster. This happens quite often due
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to reloading of operands[0]. In that case, flags are set correctly
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due to the load instruction. */
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if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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if ((cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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|| (cc_status.value2 && rtx_equal_p (cc_status.value2, operands[0])))
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return \"beq\\t%l1\";
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else
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return \"tbeq\\t%0,%l1\";
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@ -5924,7 +5930,8 @@
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"TARGET_M6812"
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"*
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{
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if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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if ((cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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|| (cc_status.value2 && rtx_equal_p (cc_status.value2, operands[0])))
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return \"bne\\t%l1\";
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else
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return \"tbne\\t%0,%l1\";
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@ -5942,7 +5949,8 @@
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"TARGET_M6812"
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"*
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{
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if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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if ((cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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|| (cc_status.value2 && rtx_equal_p (cc_status.value2, operands[0])))
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return \"beq\\t%l1\";
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else
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return \"tbeq\\tb,%l1\";
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@ -5957,7 +5965,8 @@
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"TARGET_M6812"
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"*
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{
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if (cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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if ((cc_status.value1 && rtx_equal_p (cc_status.value1, operands[0]))
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|| (cc_status.value2 && rtx_equal_p (cc_status.value2, operands[0])))
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return \"bne\\t%l1\";
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else
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return \"tbne\\tb,%l1\";
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@ -6425,6 +6434,65 @@
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(set (match_dup 0) (plus:HI (match_dup 0) (match_dup 1)))]
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"")
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;;
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;; Remove a possible move before a compare instruction when that
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;; move will go in a dead register. Compare with the source then.
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(match_operand:HI 1 "hard_reg_operand" ""))
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(set (cc0)
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(compare (match_dup 0)
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(match_operand:HI 2 "cmp_operand" "")))]
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"(X_REG_P (operands[1]) || Y_REG_P (operands[1]))
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&& peep2_reg_dead_p (2, operands[0])
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&& !reg_mentioned_p (operands[0], operands[2])"
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[(set (cc0) (compare (match_dup 1) (match_dup 2)))]
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"")
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;;
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;; Optimize an address register increment and a compare to use
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;; a PRE_INC or PRE_DEC addressing mode (disabled on the compare insn
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;; before reload, but can be enabled after).
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;;
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(plus:HI (match_dup 0)
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(match_operand:HI 1 "const_int_operand" "")))
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(set (cc0)
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(compare (match_operand:QI 2 "hard_reg_operand" "")
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(match_operand:QI 3 "memory_operand" "")))]
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"TARGET_AUTO_INC_DEC
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&& (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1)
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&& reg_mentioned_p (operands[0], operands[3])"
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[(set (cc0) (compare (match_dup 2) (match_dup 4)))]
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"if (INTVAL (operands[1]) == 1)
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operands[4] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_INC, HImode, operands[0]));
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else
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operands[4] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_DEC, HImode, operands[0]));
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")
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(define_peephole2
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[(set (match_operand:HI 0 "hard_reg_operand" "")
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(plus:HI (match_dup 0)
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(match_operand:HI 1 "const_int_operand" "")))
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(set (cc0)
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(compare (match_operand:QI 2 "memory_operand" "")
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(match_operand:QI 3 "hard_reg_operand" "")))]
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"TARGET_AUTO_INC_DEC
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&& (INTVAL (operands[1]) == -1 || INTVAL (operands[1]) == 1)
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&& reg_mentioned_p (operands[0], operands[2])"
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[(set (cc0) (compare (match_dup 4) (match_dup 3)))]
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"if (INTVAL (operands[1]) == 1)
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operands[4] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_INC, HImode, operands[0]));
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else
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operands[4] = gen_rtx (MEM, QImode,
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gen_rtx (PRE_DEC, HImode, operands[0]));
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")
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;;
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;; This peephole catches the address computations generated by the reload
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;; pass.
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Block a user