alpha.c (alpha_comparison_operator): Don't be so strict about DImode.
* config/alpha/alpha.c (alpha_comparison_operator): Don't be so strict about DImode. (alpha_swapped_comparison_operator): Likewise. * config/alpha/alpha.md (*setne_internal): Name it. Allow any integer output mode. (*setcc_internal): Likewise. (*setcc_swapped_internal): Likewise. (*movdicc_internal, *movdicc_lbc, *movdicc_lbs): Name them. (*mov[qhs]icc_internal): New. (*mov[qhs]icc_lbc, *mov[qhs]icc_lbs): New. From-SVN: r34188
This commit is contained in:
parent
b49425e47c
commit
a0e5a544ae
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@ -1,3 +1,16 @@
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2000-05-25 Richard Henderson <rth@cygnus.com>
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* config/alpha/alpha.c (alpha_comparison_operator): Don't be
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so strict about DImode.
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(alpha_swapped_comparison_operator): Likewise.
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* config/alpha/alpha.md (*setne_internal): Name it. Allow
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any integer output mode.
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(*setcc_internal): Likewise.
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(*setcc_swapped_internal): Likewise.
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(*movdicc_internal, *movdicc_lbc, *movdicc_lbs): Name them.
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(*mov[qhs]icc_internal): New.
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(*mov[qhs]icc_lbc, *mov[qhs]icc_lbs): New.
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2000-05-25 J. David Anglin <dave@hiauly1.hia.nrc.ca>
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* vax.h (CPP_SPEC): Define __GFLOAT and GFLOAT when -mg is specified.
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@ -714,7 +714,7 @@ alpha_comparison_operator (op, mode)
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return 0;
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return (code == EQ || code == LE || code == LT
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|| (mode == DImode && (code == LEU || code == LTU)));
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|| code == LEU || code == LTU);
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}
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/* Return 1 if OP is a valid Alpha swapped comparison operator. */
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@ -732,7 +732,7 @@ alpha_swapped_comparison_operator (op, mode)
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code = swap_condition (code);
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return (code == EQ || code == LE || code == LT
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|| (mode == DImode && (code == LEU || code == LTU)));
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|| code == LEU || code == LTU);
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}
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/* Return 1 if OP is a signed comparison operation. */
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@ -2495,36 +2495,74 @@
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;; Next are all the integer comparisons, and conditional moves and branches
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;; and some of the related define_expand's and define_split's.
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(ne:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")
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(const_int 0)))]
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""
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(define_insn "*setne_internal"
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[(set (match_operand 0 "register_operand" "=r")
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(ne (match_operand:DI 1 "reg_or_8bit_operand" "rI")
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(const_int 0)))]
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"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
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&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
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&& GET_MODE (operands[0]) == GET_MODE (SET_SRC (PATTERN (insn)))"
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"cmpult $31,%1,%0"
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[(set_attr "type" "icmp")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operator:DI 1 "alpha_comparison_operator"
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(define_insn "*setcc_internal"
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[(set (match_operand 0 "register_operand" "=r")
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(match_operator 1 "alpha_comparison_operator"
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[(match_operand:DI 2 "reg_or_0_operand" "rJ")
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(match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
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""
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"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
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&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
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&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
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"cmp%C1 %r2,%3,%0"
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[(set_attr "type" "icmp")])
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(define_insn ""
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[(set (match_operand:DI 0 "register_operand" "=r")
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(match_operator:DI 1 "alpha_swapped_comparison_operator"
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(define_insn "*setcc_swapped_internal"
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[(set (match_operand 0 "register_operand" "=r")
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(match_operator 1 "alpha_swapped_comparison_operator"
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[(match_operand:DI 2 "reg_or_8bit_operand" "rI")
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(match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
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""
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"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
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&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
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&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
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"cmp%c1 %r3,%2,%0"
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[(set_attr "type" "icmp")])
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;; This pattern exists so conditional moves of SImode values are handled.
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;; Comparisons are still done in DImode though.
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;; The mode folding trick can't be used with const_int operands, since
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;; reload needs to know the proper mode.
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(define_insn ""
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(define_insn "*movqicc_internal"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
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(if_then_else:QI
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(match_operator 2 "signed_comparison_operator"
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[(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
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(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
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(match_operand:QI 1 "reg_or_8bit_operand" "rI,0,rI,0")
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(match_operand:QI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
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"(operands[3] == const0_rtx || operands[4] == const0_rtx)"
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"@
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cmov%C2 %r3,%1,%0
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cmov%D2 %r3,%5,%0
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cmov%c2 %r4,%1,%0
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cmov%d2 %r4,%5,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movhicc_internal"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(if_then_else:HI
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(match_operator 2 "signed_comparison_operator"
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[(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
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(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
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(match_operand:HI 1 "reg_or_8bit_operand" "rI,0,rI,0")
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(match_operand:HI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
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"(operands[3] == const0_rtx || operands[4] == const0_rtx)"
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"@
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cmov%C2 %r3,%1,%0
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cmov%D2 %r3,%5,%0
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cmov%c2 %r4,%1,%0
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cmov%d2 %r4,%5,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movsicc_internal"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
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(if_then_else:SI
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(match_operator 2 "signed_comparison_operator"
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@ -2532,7 +2570,7 @@
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(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
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(match_operand:SI 1 "reg_or_8bit_operand" "rI,0,rI,0")
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(match_operand:SI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
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"operands[3] == const0_rtx || operands[4] == const0_rtx"
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"(operands[3] == const0_rtx || operands[4] == const0_rtx)"
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"@
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cmov%C2 %r3,%1,%0
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cmov%D2 %r3,%5,%0
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@ -2540,7 +2578,7 @@
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cmov%d2 %r4,%5,%0"
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[(set_attr "type" "icmov")])
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(define_insn ""
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(define_insn "*movdicc_internal"
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[(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
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(if_then_else:DI
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(match_operator 2 "signed_comparison_operator"
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@ -2548,7 +2586,7 @@
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(match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
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(match_operand:DI 1 "reg_or_8bit_operand" "rI,0,rI,0")
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(match_operand:DI 5 "reg_or_8bit_operand" "0,rI,0,rI")))]
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"operands[3] == const0_rtx || operands[4] == const0_rtx"
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"(operands[3] == const0_rtx || operands[4] == const0_rtx)"
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"@
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cmov%C2 %r3,%1,%0
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cmov%D2 %r3,%5,%0
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cmov%d2 %r4,%5,%0"
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[(set_attr "type" "icmov")])
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(define_insn ""
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(define_insn "*movqicc_lbc"
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[(set (match_operand:QI 0 "register_operand" "=r,r")
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(if_then_else:QI
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(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbc %r2,%1,%0
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cmovlbs %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movhicc_lbc"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(if_then_else:HI
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(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbc %r2,%1,%0
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cmovlbs %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movsicc_lbc"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(if_then_else:SI
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(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbc %r2,%1,%0
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cmovlbs %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movdicc_lbc"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(if_then_else:DI
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(eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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cmovlbs %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn ""
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(define_insn "*movqicc_lbs"
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[(set (match_operand:QI 0 "register_operand" "=r,r")
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(if_then_else:QI
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(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbs %r2,%1,%0
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cmovlbc %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movhicc_lbs"
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[(set (match_operand:HI 0 "register_operand" "=r,r")
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(if_then_else:HI
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(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbs %r2,%1,%0
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cmovlbc %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movsicc_lbs"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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(if_then_else:SI
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(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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(const_int 1)
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(const_int 0))
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(const_int 0))
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(match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
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(match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
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""
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"@
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cmovlbs %r2,%1,%0
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cmovlbc %r2,%3,%0"
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[(set_attr "type" "icmov")])
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(define_insn "*movdicc_lbs"
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[(set (match_operand:DI 0 "register_operand" "=r,r")
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(if_then_else:DI
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(ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
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