parent
dcfb710401
commit
a0fbc3a981
29
gcc/flow.c
29
gcc/flow.c
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@ -2148,16 +2148,16 @@ find_auto_inc (needed, x, insn)
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reg_n_calls_crossed[regno]++;
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}
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if (win)
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if (win
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/* If we have found a suitable auto-increment, do
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POST_INC around the register here, and patch out the
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increment instruction that follows. */
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&& validate_change (insn, &XEXP (x, 0),
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gen_rtx ((INTVAL (XEXP (y, 1)) == size
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? (offset ? PRE_INC : POST_INC)
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: (offset ? PRE_DEC : POST_DEC)),
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Pmode, addr), 0))
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{
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/* We have found a suitable auto-increment: do POST_INC around
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the register here, and patch out the increment instruction
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that follows. */
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XEXP (x, 0) = gen_rtx ((INTVAL (XEXP (y, 1)) == size
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? (offset ? PRE_INC : POST_INC)
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: (offset ? PRE_DEC : POST_DEC)),
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Pmode, addr);
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/* Record that this insn has an implicit side effect. */
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REG_NOTES (insn)
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= gen_rtx (EXPR_LIST, REG_INC, addr, REG_NOTES (insn));
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@ -2617,10 +2617,13 @@ try_pre_increment (insn, reg, amount)
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if (GET_MODE_SIZE (GET_MODE (use)) != (amount > 0 ? amount : - amount))
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return 0;
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XEXP (use, 0) = gen_rtx (amount > 0
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? (do_post ? POST_INC : PRE_INC)
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: (do_post ? POST_DEC : PRE_DEC),
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Pmode, reg);
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/* See if this combination of instruction and addressing mode exists. */
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if (! validate_change (insn, &XEXP (use, 0),
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gen_rtx (amount > 0
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? (do_post ? POST_INC : PRE_INC)
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: (do_post ? POST_DEC : PRE_DEC),
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Pmode, reg), 0))
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return 0;
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/* Record that this insn now has an implicit side effect on X. */
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REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, reg, REG_NOTES (insn));
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