(all patterns): Use GEN_INT instead of gen_rtx to get const_ints.
Avoid double-negative "! NON_*" constructs for clarity. Pass NULL_PTR as null parameter instead of 0. (sqrtM2): Patterns are only valid if IEEE FP or -ffast-math. (sinM2,cosM2): New patterns. (zero_extract test): New pattern. From-SVN: r1982
This commit is contained in:
James Van Artsdalen
parent
435defd182
commit
a199fdd675
@ -52,7 +52,10 @@
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;; operand 1 is a register containing the value to scan for. The mode
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;; of the scas opcode will be the same as the mode of this operand.
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;; operand 2 is the known alignment of operand 0.
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;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
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;; operand 0 is the argument for `sin'.
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;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
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;; operand 0 is the argument for `cos'.
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;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM".
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;; But restricting MEM here would mean that gcc could not remove a redundant
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@ -427,7 +430,7 @@
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/* For small integers, we may actually use testb. */
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if (GET_CODE (operands[1]) == CONST_INT
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
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&& ! NON_QI_REG_P (operands[0]))
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&& (! REG_P (operands[0]) || QI_REG_P (operands[0])))
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{
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/* We may set the sign bit spuriously. */
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@ -440,8 +443,7 @@
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if ((INTVAL (operands[1]) & ~0xff00) == 0)
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{
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cc_status.flags |= CC_NOT_NEGATIVE;
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) >> 8);
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operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
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if (QI_REG_P (operands[0]))
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return AS2 (test%B0,%1,%h0);
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@ -456,9 +458,7 @@
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&& (INTVAL (operands[1]) & ~0xff0000) == 0)
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{
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cc_status.flags |= CC_NOT_NEGATIVE;
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) >> 16);
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operands[1] = GEN_INT (INTVAL (operands[1]) >> 16);
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operands[0] = adj_offsettable_operand (operands[0], 2);
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return AS2 (test%B0,%1,%b0);
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}
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@ -466,9 +466,7 @@
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if (GET_CODE (operands[0]) == MEM
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&& (INTVAL (operands[1]) & ~0xff000000) == 0)
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{
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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(INTVAL (operands[1]) >> 24) & 0xff);
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operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff);
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operands[0] = adj_offsettable_operand (operands[0], 3);
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return AS2 (test%B0,%1,%b0);
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}
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@ -489,14 +487,13 @@
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{
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if (GET_CODE (operands[1]) == CONST_INT
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))
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&& ! NON_QI_REG_P (operands[0]))
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&& (! REG_P (operands[0]) || QI_REG_P (operands[0])))
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{
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if ((INTVAL (operands[1]) & 0xff00) == 0)
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{
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/* ??? This might not be necessary. */
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if (INTVAL (operands[1]) & 0xffff0000)
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[1]) & 0xff);
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operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
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/* We may set the sign bit spuriously. */
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cc_status.flags |= CC_NOT_NEGATIVE;
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@ -505,8 +502,7 @@
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if ((INTVAL (operands[1]) & 0xff) == 0)
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{
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operands[1] = gen_rtx (CONST_INT, VOIDmode,
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(INTVAL (operands[1]) >> 8) & 0xff);
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operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff);
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if (QI_REG_P (operands[0]))
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return AS2 (test%B0,%1,%h0);
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@ -772,7 +768,7 @@
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abort ();
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xops[0] = AT_SP (SFmode);
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
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xops[1] = GEN_INT (4);
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xops[2] = stack_pointer_rtx;
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output_asm_insn (AS2 (sub%L2,%1,%2), xops);
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@ -853,7 +849,7 @@
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rtx xops[3];
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xops[0] = AT_SP (SFmode);
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 8);
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xops[1] = GEN_INT (8);
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xops[2] = stack_pointer_rtx;
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output_asm_insn (AS2 (sub%L2,%1,%2), xops);
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@ -974,7 +970,7 @@
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{
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rtx xops[2];
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xops[0] = operands[0];
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xffff);
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xops[1] = GEN_INT (0xffff);
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output_asm_insn (AS2 (and%L0,%1,%k0), xops);
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RET;
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}
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@ -998,7 +994,7 @@
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{
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rtx xops[2];
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xops[0] = operands[0];
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff);
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xops[1] = GEN_INT (0xff);
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output_asm_insn (AS2 (and%L0,%1,%k0), xops);
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RET;
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}
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@ -1022,7 +1018,7 @@
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{
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rtx xops[2];
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xops[0] = operands[0];
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 0xff);
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xops[1] = GEN_INT (0xff);
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output_asm_insn (AS2 (and%L0,%1,%k0), xops);
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RET;
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}
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@ -1822,8 +1818,7 @@
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return AS2 (mov%B0,%2,%b0);
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}
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) & 0xff);
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
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return AS2 (and%B0,%2,%b0);
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}
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@ -1837,8 +1832,7 @@
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return AS2 (mov%B0,%2,%h0);
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}
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) >> 8);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
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return AS2 (and%B0,%2,%h0);
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}
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@ -1863,7 +1857,7 @@
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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{
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/* Can we ignore the upper byte? */
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if (! NON_QI_REG_P (operands[0])
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if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
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&& (INTVAL (operands[2]) & 0xff00) == 0xff00)
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{
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CC_STATUS_INIT;
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@ -1874,8 +1868,7 @@
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return AS2 (mov%B0,%2,%b0);
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}
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) & 0xff);
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
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return AS2 (and%B0,%2,%b0);
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}
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@ -1891,8 +1884,7 @@
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return AS2 (mov%B0,%2,%h0);
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}
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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(INTVAL (operands[2]) >> 8) & 0xff);
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operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
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return AS2 (and%B0,%2,%h0);
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}
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}
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@ -1944,7 +1936,8 @@
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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{
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if (! NON_QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff) == 0)
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if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
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&& (INTVAL (operands[2]) & ~0xff) == 0)
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{
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CC_STATUS_INIT;
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@ -1957,8 +1950,7 @@
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if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) >> 8);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
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if (INTVAL (operands[2]) == 0xff)
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return AS2 (mov%B0,%2,%h0);
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@ -1981,13 +1973,12 @@
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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{
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/* Can we ignore the upper byte? */
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if (! NON_QI_REG_P (operands[0])
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if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
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&& (INTVAL (operands[2]) & 0xff00) == 0)
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{
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CC_STATUS_INIT;
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if (INTVAL (operands[2]) & 0xffff0000)
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) & 0xffff);
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
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if (INTVAL (operands[2]) == 0xff)
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return AS2 (mov%B0,%2,%b0);
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@ -2001,8 +1992,7 @@
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&& (INTVAL (operands[2]) & 0xff) == 0)
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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(INTVAL (operands[2]) >> 8) & 0xff);
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operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
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if (INTVAL (operands[2]) == 0xff)
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return AS2 (mov%B0,%2,%h0);
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@ -2034,7 +2024,8 @@
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if (GET_CODE (operands[2]) == CONST_INT
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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{
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if (! NON_QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff) == 0)
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if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
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&& (INTVAL (operands[2]) & ~0xff) == 0)
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{
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CC_STATUS_INIT;
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@ -2047,8 +2038,7 @@
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if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0)
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) >> 8);
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operands[2] = GEN_INT (INTVAL (operands[2]) >> 8);
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if (INTVAL (operands[2]) == 0xff)
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return AS1 (not%B0,%h0);
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@ -2071,13 +2061,12 @@
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&& ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
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{
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/* Can we ignore the upper byte? */
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if (! NON_QI_REG_P (operands[0])
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if ((! REG_P (operands[0]) || QI_REG_P (operands[0]))
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&& (INTVAL (operands[2]) & 0xff00) == 0)
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{
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CC_STATUS_INIT;
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if (INTVAL (operands[2]) & 0xffff0000)
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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INTVAL (operands[2]) & 0xffff);
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operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
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if (INTVAL (operands[2]) == 0xff)
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return AS1 (not%B0,%b0);
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@ -2091,8 +2080,7 @@
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&& (INTVAL (operands[2]) & 0xff) == 0)
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{
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CC_STATUS_INIT;
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operands[2] = gen_rtx (CONST_INT, VOIDmode,
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(INTVAL (operands[2]) >> 8) & 0xff);
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operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
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if (INTVAL (operands[2]) == 0xff)
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return AS1 (not%B0,%h0);
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@ -2192,21 +2180,59 @@
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(define_insn "sqrtsf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(sqrt:SF (match_operand:SF 1 "general_operand" "0")))]
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"TARGET_80387"
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsqrt")
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(define_insn "sqrtdf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(sqrt:DF (match_operand:DF 1 "general_operand" "0")))]
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"TARGET_80387"
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsqrt")
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(sqrt:DF (float_extend:DF
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(match_operand:SF 1 "general_operand" "0"))))]
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"TARGET_80387"
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsqrt")
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(define_insn "sindf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsin")
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(define_insn "sinsf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsin")
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(float_extend:DF
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(match_operand:SF 1 "register_operand" "0"))] 1))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fsin")
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(define_insn "cosdf2"
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fcos")
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(define_insn "cossf2"
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[(set (match_operand:SF 0 "register_operand" "=f")
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(unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fcos")
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(define_insn ""
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[(set (match_operand:DF 0 "register_operand" "=f")
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(unspec:DF [(float_extend:DF
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(match_operand:SF 1 "register_operand" "0"))] 2))]
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"TARGET_80387 && (TARGET_IEEE_FP || flag_fast_math)"
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"fcos")
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;;- one complement instructions
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@ -2297,8 +2323,7 @@
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if (INTVAL (xops[0]) > 32)
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{
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xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32);
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xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
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output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */
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}
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}
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@ -2335,7 +2360,7 @@
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output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops);
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output_asm_insn (AS2 (sal%L2,%0,%2), xops);
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */
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xops[1] = GEN_INT (7); /* shift count & 1 */
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output_asm_insn (AS2 (shr%B0,%1,%0), xops);
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@ -2367,8 +2392,7 @@
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{
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CC_STATUS_INIT;
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operands[1] = gen_rtx (MULT, SImode, operands[1],
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gen_rtx (CONST_INT, VOIDmode,
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1 << INTVAL (operands[2])));
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GEN_INT (1 << INTVAL (operands[2])));
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return AS2 (lea%L0,%a1,%0);
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}
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}
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@ -2455,14 +2479,13 @@
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if (INTVAL (xops[0]) > 31)
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{
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 31);
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xops[1] = GEN_INT (31);
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output_asm_insn (AS2 (mov%L2,%3,%2), xops);
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output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */
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if (INTVAL (xops[0]) > 32)
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{
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xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32);
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xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
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output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */
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}
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}
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@ -2500,7 +2523,7 @@
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output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
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output_asm_insn (AS2 (sar%L3,%0,%3), xops);
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xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */
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xops[1] = GEN_INT (7); /* shift count & 1 */
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output_asm_insn (AS2 (shr%B0,%1,%0), xops);
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@ -2597,8 +2620,7 @@
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if (INTVAL (xops[0]) > 32)
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{
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xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xops[0]) - 32);
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|
||||
xops[0] = GEN_INT (INTVAL (xops[0]) - 32);
|
||||
output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */
|
||||
}
|
||||
}
|
||||
@ -2636,7 +2658,7 @@
|
||||
output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops);
|
||||
output_asm_insn (AS2 (shr%L3,%0,%3), xops);
|
||||
|
||||
xops[1] = gen_rtx (CONST_INT, VOIDmode, 7); /* shift count & 1 */
|
||||
xops[1] = GEN_INT (7); /* shift count & 1 */
|
||||
|
||||
output_asm_insn (AS2 (shr%B0,%1,%0), xops);
|
||||
|
||||
@ -2782,11 +2804,9 @@
|
||||
if (GET_CODE (operands[3]) == CONST_INT)
|
||||
{
|
||||
unsigned int mask = (1 << INTVAL (operands[1])) - 1;
|
||||
operands[1] = gen_rtx (CONST_INT, VOIDmode,
|
||||
~(mask << INTVAL (operands[2])));
|
||||
operands[1] = GEN_INT (~(mask << INTVAL (operands[2])));
|
||||
output_asm_insn (AS2 (and%L0,%1,%0), operands);
|
||||
operands[3] = gen_rtx (CONST_INT, VOIDmode,
|
||||
INTVAL (operands[3]) << INTVAL (operands[2]));
|
||||
operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2]));
|
||||
output_asm_insn (AS2 (or%L0,%3,%0), operands);
|
||||
}
|
||||
else
|
||||
@ -2795,8 +2815,7 @@
|
||||
if (INTVAL (operands[2]))
|
||||
output_asm_insn (AS2 (ror%L0,%2,%0), operands);
|
||||
output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands);
|
||||
operands[2] = gen_rtx (CONST_INT, VOIDmode,
|
||||
BITS_PER_WORD
|
||||
operands[2] = GEN_INT (BITS_PER_WORD
|
||||
- INTVAL (operands[1]) - INTVAL (operands[2]));
|
||||
if (INTVAL (operands[2]))
|
||||
output_asm_insn (AS2 (ror%L0,%2,%0), operands);
|
||||
@ -2912,6 +2931,69 @@
|
||||
;; don't allow a MEM in the operand predicate without allowing it in the
|
||||
;; constraint.
|
||||
|
||||
;; ??? All bets are off if operand 0 is a volatile MEM reference.
|
||||
|
||||
(define_insn ""
|
||||
[(set (cc0) (zero_extract (match_operand 0 "general_operand" "rm")
|
||||
(match_operand:SI 1 "const_int_operand" "n")
|
||||
(match_operand:SI 2 "const_int_operand" "n")))]
|
||||
"GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
|
||||
&& GET_MODE_SIZE (GET_MODE (operands[0])) <= 4
|
||||
&& (GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0]))"
|
||||
"*
|
||||
{
|
||||
unsigned int mask;
|
||||
|
||||
mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]);
|
||||
operands[1] = GEN_INT (mask);
|
||||
|
||||
if (! REG_P (operands[0]) || QI_REG_P (operands[0]))
|
||||
{
|
||||
/* We may set the sign bit spuriously. */
|
||||
|
||||
if ((mask & ~0xff) == 0)
|
||||
{
|
||||
cc_status.flags |= CC_NOT_NEGATIVE;
|
||||
return AS2 (test%B0,%1,%b0);
|
||||
}
|
||||
|
||||
if ((mask & ~0xff00) == 0)
|
||||
{
|
||||
cc_status.flags |= CC_NOT_NEGATIVE;
|
||||
operands[1] = GEN_INT (mask >> 8);
|
||||
|
||||
if (QI_REG_P (operands[0]))
|
||||
return AS2 (test%B0,%1,%h0);
|
||||
else
|
||||
{
|
||||
operands[0] = adj_offsettable_operand (operands[0], 1);
|
||||
return AS2 (test%B0,%1,%b0);
|
||||
}
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0)
|
||||
{
|
||||
cc_status.flags |= CC_NOT_NEGATIVE;
|
||||
operands[1] = GEN_INT (mask >> 16);
|
||||
operands[0] = adj_offsettable_operand (operands[0], 2);
|
||||
return AS2 (test%B0,%1,%b0);
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0)
|
||||
{
|
||||
cc_status.flags |= CC_NOT_NEGATIVE;
|
||||
operands[1] = GEN_INT (mask >> 24);
|
||||
operands[0] = adj_offsettable_operand (operands[0], 3);
|
||||
return AS2 (test%B0,%1,%b0);
|
||||
}
|
||||
}
|
||||
|
||||
if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
|
||||
return AS2 (test%L0,%1,%0);
|
||||
|
||||
return AS2 (test%L1,%0,%1);
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
[(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r")
|
||||
(const_int 1)
|
||||
@ -2997,7 +3079,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (sete,%0);
|
||||
|
||||
OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0);
|
||||
OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_expand "sgtu"
|
||||
@ -3093,7 +3175,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (setb,%0);
|
||||
|
||||
OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0);
|
||||
OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_expand "sleu"
|
||||
@ -3201,7 +3283,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (je,%l0);
|
||||
|
||||
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0);
|
||||
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_expand "bgtu"
|
||||
@ -3333,7 +3415,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (jb,%l0);
|
||||
|
||||
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0);
|
||||
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_expand "bleu"
|
||||
@ -3399,7 +3481,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (jne,%l0);
|
||||
|
||||
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0);
|
||||
OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
@ -3471,7 +3553,7 @@
|
||||
if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387))
|
||||
return AS1 (jae,%l0);
|
||||
|
||||
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0);
|
||||
OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR);
|
||||
}")
|
||||
|
||||
(define_insn ""
|
||||
@ -3825,7 +3907,7 @@
|
||||
{
|
||||
if (INTVAL (operands[2]) & ~0x03)
|
||||
{
|
||||
xops[0] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
|
||||
xops[0] = GEN_INT (INTVAL (operands[2]) >> 2);
|
||||
xops[1] = operands[4];
|
||||
|
||||
output_asm_insn (AS2 (mov%L1,%0,%1), xops);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user