S/390: Remove code duplication in vec_* comparison expanders
s390.md uses a lot of near-identical expanders that perform dispatching to other expanders based on operand types. Since the following patch would require even more of these, avoid copy-pasting the code by generating these expanders using an iterator. gcc/ChangeLog: 2019-10-01 Ilya Leoshkevich <iii@linux.ibm.com> PR target/77918 * config/s390/s390.c (s390_expand_vec_compare): Use gen_vec_cmpordered and gen_vec_cmpunordered. * config/s390/vector.md (vec_cmpuneq, vec_cmpltgt, vec_ordered, vec_unordered): Delete. (vec_ordered<mode>): Rename to vec_cmpordered<mode>. (vec_unordered<mode>): Rename to vec_cmpunordered<mode>. (VEC_CMP_EXPAND): New iterator for the generic dispatcher. (vec_cmp<code>): Generic dispatcher. From-SVN: r276409
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@ -1,3 +1,15 @@
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2019-10-01 Ilya Leoshkevich <iii@linux.ibm.com>
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PR target/77918
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* config/s390/s390.c (s390_expand_vec_compare): Use
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gen_vec_cmpordered and gen_vec_cmpunordered.
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* config/s390/vector.md (vec_cmpuneq, vec_cmpltgt, vec_ordered,
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vec_unordered): Delete.
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(vec_ordered<mode>): Rename to vec_cmpordered<mode>.
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(vec_unordered<mode>): Rename to vec_cmpunordered<mode>.
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(VEC_CMP_EXPAND): New iterator for the generic dispatcher.
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(vec_cmp<code>): Generic dispatcher.
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2019-10-01 Ilya Leoshkevich <iii@linux.ibm.com>
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PR target/77918
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@ -6523,10 +6523,10 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond,
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emit_insn (gen_vec_cmpltgt (target, cmp_op1, cmp_op2));
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return;
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case ORDERED:
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emit_insn (gen_vec_ordered (target, cmp_op1, cmp_op2));
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emit_insn (gen_vec_cmpordered (target, cmp_op1, cmp_op2));
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return;
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case UNORDERED:
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emit_insn (gen_vec_unordered (target, cmp_op1, cmp_op2));
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emit_insn (gen_vec_cmpunordered (target, cmp_op1, cmp_op2));
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return;
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default: break;
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}
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@ -1472,22 +1472,6 @@
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operands[3] = gen_reg_rtx (<tointvec>mode);
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})
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(define_expand "vec_cmpuneq"
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[(match_operand 0 "register_operand" "")
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(match_operand 1 "register_operand" "")
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(match_operand 2 "register_operand" "")]
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"TARGET_VX"
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{
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if (GET_MODE (operands[1]) == V4SFmode)
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emit_insn (gen_vec_cmpuneqv4sf (operands[0], operands[1], operands[2]));
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else if (GET_MODE (operands[1]) == V2DFmode)
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emit_insn (gen_vec_cmpuneqv2df (operands[0], operands[1], operands[2]));
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else
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gcc_unreachable ();
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DONE;
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})
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; LTGT a <> b -> a > b | b > a
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(define_expand "vec_cmpltgt<mode>"
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[(set (match_operand:<tointvec> 0 "register_operand" "=v")
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@ -1500,24 +1484,8 @@
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operands[3] = gen_reg_rtx (<tointvec>mode);
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})
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(define_expand "vec_cmpltgt"
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[(match_operand 0 "register_operand" "")
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(match_operand 1 "register_operand" "")
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(match_operand 2 "register_operand" "")]
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"TARGET_VX"
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{
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if (GET_MODE (operands[1]) == V4SFmode)
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emit_insn (gen_vec_cmpltgtv4sf (operands[0], operands[1], operands[2]));
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else if (GET_MODE (operands[1]) == V2DFmode)
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emit_insn (gen_vec_cmpltgtv2df (operands[0], operands[1], operands[2]));
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else
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gcc_unreachable ();
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DONE;
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})
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; ORDERED (a, b): a >= b | b > a
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(define_expand "vec_ordered<mode>"
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(define_expand "vec_cmpordered<mode>"
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[(set (match_operand:<tointvec> 0 "register_operand" "=v")
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(ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
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(match_operand:VFT 2 "register_operand" "v")))
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@ -1528,45 +1496,32 @@
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operands[3] = gen_reg_rtx (<tointvec>mode);
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})
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(define_expand "vec_ordered"
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[(match_operand 0 "register_operand" "")
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(match_operand 1 "register_operand" "")
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(match_operand 2 "register_operand" "")]
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"TARGET_VX"
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{
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if (GET_MODE (operands[1]) == V4SFmode)
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emit_insn (gen_vec_orderedv4sf (operands[0], operands[1], operands[2]));
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else if (GET_MODE (operands[1]) == V2DFmode)
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emit_insn (gen_vec_orderedv2df (operands[0], operands[1], operands[2]));
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else
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gcc_unreachable ();
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DONE;
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})
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; UNORDERED (a, b): !ORDERED (a, b)
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(define_expand "vec_unordered<mode>"
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(define_expand "vec_cmpunordered<mode>"
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[(match_operand:<tointvec> 0 "register_operand" "=v")
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(match_operand:VFT 1 "register_operand" "v")
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(match_operand:VFT 2 "register_operand" "v")]
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"TARGET_VX"
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{
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emit_insn (gen_vec_ordered<mode> (operands[0], operands[1], operands[2]));
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emit_insn (gen_vec_cmpordered<mode> (operands[0], operands[1], operands[2]));
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emit_insn (gen_rtx_SET (operands[0],
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gen_rtx_NOT (<tointvec>mode, operands[0])));
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DONE;
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})
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(define_expand "vec_unordered"
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(define_code_iterator VEC_CMP_EXPAND
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[uneq ltgt ordered unordered])
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(define_expand "vec_cmp<code>"
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[(match_operand 0 "register_operand" "")
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(match_operand 1 "register_operand" "")
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(match_operand 2 "register_operand" "")]
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(VEC_CMP_EXPAND (match_operand 1 "register_operand" "")
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(match_operand 2 "register_operand" ""))]
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"TARGET_VX"
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{
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if (GET_MODE (operands[1]) == V4SFmode)
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emit_insn (gen_vec_unorderedv4sf (operands[0], operands[1], operands[2]));
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emit_insn (gen_vec_cmp<code>v4sf (operands[0], operands[1], operands[2]));
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else if (GET_MODE (operands[1]) == V2DFmode)
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emit_insn (gen_vec_unorderedv2df (operands[0], operands[1], operands[2]));
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emit_insn (gen_vec_cmp<code>v2df (operands[0], operands[1], operands[2]));
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else
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gcc_unreachable ();
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