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i386-protos.h (ix86_agi_dependent): New. 

2009-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386-protos.h (ix86_agi_dependent): New.

	* config/i386/i386.c (ix86_agi_dependent): Rewrite.
	(ix86_adjust_cost): Updated.

From-SVN: r145235
This commit is contained in:
H.J. Lu 2009-03-29 14:57:02 +00:00 committed by H.J. Lu
parent 3379ae7f3b
commit a24078b219
3 changed files with 39 additions and 38 deletions
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7
gcc/ChangeLog
View File

@ -1,3 +1,10 @@
2009-03-29 H.J. Lu <hongjiu.lu@intel.com>
* config/i386/i386-protos.h (ix86_agi_dependent): New.
* config/i386/i386.c (ix86_agi_dependent): Rewrite.
(ix86_adjust_cost): Updated.
2009-03-29 Jan Hubicka <jh@suse.cz>
PR middle-end/28850

1
gcc/config/i386/i386-protos.h
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@ -85,6 +85,7 @@ extern void ix86_fixup_binary_operands_no_copy (enum rtx_code,
extern void ix86_expand_binary_operator (enum rtx_code,
enum machine_mode, rtx[]);
extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn);
extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,
rtx[]);
extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx);

69
gcc/config/i386/i386.c
View File

@ -19070,41 +19070,21 @@ ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
return 1;
}
/* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
address with operands set by DEP_INSN. */
/* Return true iff USE_INSN has a memory address with operands set by
SET_INSN. */
static int
ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
bool
ix86_agi_dependent (rtx set_insn, rtx use_insn)
{
rtx addr;
if (insn_type == TYPE_LEA
&& TARGET_PENTIUM)
{
addr = PATTERN (insn);
if (GET_CODE (addr) == PARALLEL)
addr = XVECEXP (addr, 0, 0);
gcc_assert (GET_CODE (addr) == SET);
addr = SET_SRC (addr);
}
else
{
int i;
extract_insn_cached (insn);
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (MEM_P (recog_data.operand[i]))
{
addr = XEXP (recog_data.operand[i], 0);
goto found;
}
return 0;
found:;
}
return modified_in_p (addr, dep_insn);
int i;
extract_insn_cached (use_insn);
for (i = recog_data.n_operands - 1; i >= 0; --i)
if (MEM_P (recog_data.operand[i]))
{
rtx addr = XEXP (recog_data.operand[i], 0);
return modified_in_p (addr, set_insn) != 0;
}
return false;
}
static int
@ -19132,7 +19112,20 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
{
case PROCESSOR_PENTIUM:
/* Address Generation Interlock adds a cycle of latency. */
if (ix86_agi_dependent (insn, dep_insn, insn_type))
if (insn_type == TYPE_LEA)
{
rtx addr = PATTERN (insn);
if (GET_CODE (addr) == PARALLEL)
addr = XVECEXP (addr, 0, 0);
gcc_assert (GET_CODE (addr) == SET);
addr = SET_SRC (addr);
if (modified_in_p (addr, dep_insn))
cost += 1;
}
else if (ix86_agi_dependent (dep_insn, insn))
cost += 1;
/* ??? Compares pair with jump/setcc. */
@ -19142,7 +19135,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
/* Floating point stores require value to be ready one cycle earlier. */
if (insn_type == TYPE_FMOV
&& get_attr_memory (insn) == MEMORY_STORE
&& !ix86_agi_dependent (insn, dep_insn, insn_type))
&& !ix86_agi_dependent (dep_insn, insn))
cost += 1;
break;
@ -19165,7 +19158,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependent (insn, dep_insn, insn_type))
&& !ix86_agi_dependent (dep_insn, insn))
{
/* Claim moves to take one cycle, as core can issue one load
at time and the next load can start cycle later. */
@ -19194,7 +19187,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependent (insn, dep_insn, insn_type))
&& !ix86_agi_dependent (dep_insn, insn))
{
/* Claim moves to take one cycle, as core can issue one load
at time and the next load can start cycle later. */
@ -19219,7 +19212,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
in parallel with previous instruction in case
previous instruction is not needed to compute the address. */
if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
&& !ix86_agi_dependent (insn, dep_insn, insn_type))
&& !ix86_agi_dependent (dep_insn, insn))
{
enum attr_unit unit = get_attr_unit (insn);
int loadcost = 3;