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arm.c (neon_vdup_constant): Expand into canonical RTL instead of an unspec.

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2010-07-02  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/
	* config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL
	instead of an unspec.
	(neon_expand_vector_init): Likewise.
	* config/arm/neon.md (UNSPEC_VCOMBINE): Delete.
	(UNSPEC_VDUP_LANE): Delete.
	(UNSPEC VDUP_N): Delete.
	(UNSPEC_VGET_HIGH): Delete.
	(UNSPEC_VGET_LANE): Delete.
	(UNSPEC_VGET_LOW): Delete.
	(UNSPEC_VMVN): Delete.
	(UNSPEC_VSET_LANE): Delete.
	(V_double_vector_mode): New.
	(vec_set<mode>_internal): Make code emitted match that for the
	corresponding intrinsics.
	(vec_setv2di_internal): Likewise.
	(neon_vget_lanedi): Rewrite to expand into emit_move_insn.
	(neon_vget_lanev2di): Rewrite to expand into vec_extractv2di.
	(neon_vset_lane<mode>): Combine double and quad patterns and
	expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE.
	(neon_vset_lanedi): Rewrite to expand into emit_move_insn.
	(neon_vdup_n<mode>): Rewrite RTL without unspec.
	(neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn.
	(neon_vdup_nv2di): Rewrite RTL without unspec and merge with
	with neon_vdup_lanev2di, adjusting the pattern from the latter
	to be predicable for consistency.
	(neon_vdup_lane<mode>_internal): New.
	(neon_vdup_lane<mode>): Turn into a define_expand and rewrite
	to avoid using an unspec.
	(neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec.
	(neon_vdup_lanev2di): Turn into a define_expand.
	(neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE.
	(neon_vget_high<mode>): Replace with....
	(neon_vget_highv16qi): New pattern using canonical RTL.
	(neon_vget_highv8hi): Likewise.
	(neon_vget_highv4si): Likewise.
	(neon_vget_highv4sf): Likewise.
	(neon_vget_highv2di): Likewise.
	(neon_vget_low<mode>): Replace with....
	(neon_vget_lowv16qi): New pattern using canonical RTL.
	(neon_vget_lowv8hi): Likewise.
	(neon_vget_lowv4si): Likewise.
	(neon_vget_lowv4sf): Likewise.
	(neon_vget_lowv2di): Likewise.

	* config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress
	test for this emitting vmov.
	(Vset_lane): Likewise.
	(Vdup_n): Likewise.
	(Vmov_n): Likewise.

	* doc/arm-neon-intrinsics.texi: Regenerated.

	gcc/testsuite/
	* gcc.target/arm/neon/vdup_ns64.c: Regenerated.
	* gcc.target/arm/neon/vdup_nu64.c: Regenerated.
	* gcc.target/arm/neon/vdupQ_ns64.c: Regenerated.
	* gcc.target/arm/neon/vdupQ_nu64.c: Regenerated.
	* gcc.target/arm/neon/vmov_ns64.c: Regenerated.
	* gcc.target/arm/neon/vmov_nu64.c: Regenerated.
	* gcc.target/arm/neon/vmovQ_ns64.c: Regenerated.
	* gcc.target/arm/neon/vmovQ_nu64.c: Regenerated.
	* gcc.target/arm/neon/vget_lanes64.c: Regenerated.
	* gcc.target/arm/neon/vget_laneu64.c: Regenerated.
	* gcc.target/arm/neon/vset_lanes64.c: Regenerated.
	* gcc.target/arm/neon/vset_laneu64.c: Regenerated.
	* gcc.target/arm/neon-vdup_ns64.c: New.
	* gcc.target/arm/neon-vdup_nu64.c: New.
	* gcc.target/arm/neon-vdupQ_ns64.c: New.
	* gcc.target/arm/neon-vdupQ_nu64.c: New.
	* gcc.target/arm/neon-vdupQ_lanes64.c: New.
	* gcc.target/arm/neon-vdupQ_laneu64.c: New.
	* gcc.target/arm/neon-vmov_ns64.c: New.
	* gcc.target/arm/neon-vmov_nu64.c: New.
	* gcc.target/arm/neon-vmovQ_ns64.c: New.
	* gcc.target/arm/neon-vmovQ_nu64.c: New.
	* gcc.target/arm/neon-vget_lanes64.c: New.
	* gcc.target/arm/neon-vget_laneu64.c: New.
	* gcc.target/arm/neon-vset_lanes64.c: New.
	* gcc.target/arm/neon-vset_laneu64.c: New.

From-SVN: r161720
This commit is contained in:
Sandra Loosemore 2010-07-02 10:48:04 -04:00 committed by Sandra Loosemore
parent 8c98c2a6cc
commit a277dd9b1a
32 changed files with 700 additions and 227 deletions
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54
gcc/ChangeLog
View File

@ -1,3 +1,57 @@
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
* config/arm/arm.c (neon_vdup_constant): Expand into canonical RTL
instead of an unspec.
(neon_expand_vector_init): Likewise.
* config/arm/neon.md (UNSPEC_VCOMBINE): Delete.
(UNSPEC_VDUP_LANE): Delete.
(UNSPEC VDUP_N): Delete.
(UNSPEC_VGET_HIGH): Delete.
(UNSPEC_VGET_LANE): Delete.
(UNSPEC_VGET_LOW): Delete.
(UNSPEC_VMVN): Delete.
(UNSPEC_VSET_LANE): Delete.
(V_double_vector_mode): New.
(vec_set<mode>_internal): Make code emitted match that for the
corresponding intrinsics.
(vec_setv2di_internal): Likewise.
(neon_vget_lanedi): Rewrite to expand into emit_move_insn.
(neon_vget_lanev2di): Rewrite to expand into vec_extractv2di.
(neon_vset_lane<mode>): Combine double and quad patterns and
expand into vec_set<mode>_internal instead of UNSPEC_VSET_LANE.
(neon_vset_lanedi): Rewrite to expand into emit_move_insn.
(neon_vdup_n<mode>): Rewrite RTL without unspec.
(neon_vdup_ndi): Rewrite as define_expand and use emit_move_insn.
(neon_vdup_nv2di): Rewrite RTL without unspec and merge with
with neon_vdup_lanev2di, adjusting the pattern from the latter
to be predicable for consistency.
(neon_vdup_lane<mode>_internal): New.
(neon_vdup_lane<mode>): Turn into a define_expand and rewrite
to avoid using an unspec.
(neon_vdup_lanedi): Rewrite RTL pattern to avoid unspec.
(neon_vdup_lanev2di): Turn into a define_expand.
(neon_vcombine): Rewrite pattern to eliminate UNPSEC_VCOMBINE.
(neon_vget_high<mode>): Replace with....
(neon_vget_highv16qi): New pattern using canonical RTL.
(neon_vget_highv8hi): Likewise.
(neon_vget_highv4si): Likewise.
(neon_vget_highv4sf): Likewise.
(neon_vget_highv2di): Likewise.
(neon_vget_low<mode>): Replace with....
(neon_vget_lowv16qi): New pattern using canonical RTL.
(neon_vget_lowv8hi): Likewise.
(neon_vget_lowv4si): Likewise.
(neon_vget_lowv4sf): Likewise.
(neon_vget_lowv2di): Likewise.
* config/arm/neon.ml (Vget_lane): Add No_op attribute to suppress
test for this emitting vmov.
(Vset_lane): Likewise.
(Vdup_n): Likewise.
(Vmov_n): Likewise.
* doc/arm-neon-intrinsics.texi: Regenerated.
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
* config/arm/neon.md (vec_extractv2di): Correct error in register

43
gcc/config/arm/arm.c
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@ -8250,8 +8250,7 @@ neon_vdup_constant (rtx vals)
load. */
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
return gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
UNSPEC_VDUP_N);
return gen_rtx_VEC_DUPLICATE (mode, x);
}
/* Generate code to load VALS, which is a PARALLEL containing only
@ -8347,8 +8346,7 @@ neon_expand_vector_init (rtx target, rtx vals)
{
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, 0));
emit_insn (gen_rtx_SET (VOIDmode, target,
gen_rtx_UNSPEC (mode, gen_rtvec (1, x),
UNSPEC_VDUP_N)));
gen_rtx_VEC_DUPLICATE (mode, x)));
return;
}
@ -8357,7 +8355,7 @@ neon_expand_vector_init (rtx target, rtx vals)
if (n_var == 1)
{
rtx copy = copy_rtx (vals);
rtvec ops;
rtx index = GEN_INT (one_var);
/* Load constant part of vector, substitute neighboring value for
varying element. */
@ -8366,9 +8364,38 @@ neon_expand_vector_init (rtx target, rtx vals)
/* Insert variable. */
x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, one_var));
ops = gen_rtvec (3, x, target, GEN_INT (one_var));
emit_insn (gen_rtx_SET (VOIDmode, target,
gen_rtx_UNSPEC (mode, ops, UNSPEC_VSET_LANE)));
switch (mode)
{
case V8QImode:
emit_insn (gen_neon_vset_lanev8qi (target, x, target, index));
break;
case V16QImode:
emit_insn (gen_neon_vset_lanev16qi (target, x, target, index));
break;
case V4HImode:
emit_insn (gen_neon_vset_lanev4hi (target, x, target, index));
break;
case V8HImode:
emit_insn (gen_neon_vset_lanev8hi (target, x, target, index));
break;
case V2SImode:
emit_insn (gen_neon_vset_lanev2si (target, x, target, index));
break;
case V4SImode:
emit_insn (gen_neon_vset_lanev4si (target, x, target, index));
break;
case V2SFmode:
emit_insn (gen_neon_vset_lanev2sf (target, x, target, index));
break;
case V4SFmode:
emit_insn (gen_neon_vset_lanev4sf (target, x, target, index));
break;
case V2DImode:
emit_insn (gen_neon_vset_lanev2di (target, x, target, index));
break;
default:
gcc_unreachable ();
}
return;
}

438
gcc/config/arm/neon.md
View File

@ -42,16 +42,10 @@
(UNSPEC_VCLS 84)
(UNSPEC_VCLZ 85)
(UNSPEC_VCNT 86)
(UNSPEC_VCOMBINE 87)
(UNSPEC_VCVT 88)
(UNSPEC_VCVT_N 89)
(UNSPEC_VDUP_LANE 90)
(UNSPEC_VDUP_N 91)
(UNSPEC_VEOR 92)
(UNSPEC_VEXT 93)
(UNSPEC_VGET_HIGH 94)
(UNSPEC_VGET_LANE 95)
(UNSPEC_VGET_LOW 96)
(UNSPEC_VHADD 97)
(UNSPEC_VHSUB 98)
(UNSPEC_VLD1 99)
@ -87,7 +81,6 @@
(UNSPEC_VMUL_LANE 129)
(UNSPEC_VMULL_LANE 130)
(UNSPEC_VMUL_N 131)
(UNSPEC_VMVN 132)
(UNSPEC_VORN 133)
(UNSPEC_VORR 134)
(UNSPEC_VPADAL 135)
@ -125,7 +118,6 @@
(UNSPEC_VREV64 167)
(UNSPEC_VRSQRTE 168)
(UNSPEC_VRSQRTS 169)
(UNSPEC_VSET_LANE 170)
(UNSPEC_VSHL 171)
(UNSPEC_VSHLL_N 172)
(UNSPEC_VSHL_N 173)
@ -335,6 +327,14 @@
(V4HI "V2SI") (V8HI "V4SI")
(V2SI "DI") (V4SI "V2DI")])
;; Double-sized modes with the same element size.
;; Used for neon_vdup_lane, where the second operand is double-sized
;; even when the first one is quad.
(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI")
(V4SI "V2SI") (V4SF "V2SF")
(V8QI "V8QI") (V4HI "V4HI")
(V2SI "V2SI") (V2SF "V2SF")])
;; Mode of result of comparison operations (and bit-select operand 1).
(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI")
(V4HI "V4HI") (V8HI "V8HI")
@ -688,7 +688,7 @@
elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr")])
@ -714,7 +714,7 @@
operands[0] = gen_rtx_REG (<V_HALF>mode, regno + hi);
operands[2] = GEN_INT (elt);
return "vmov%?.<V_uf_sclr>\t%P0[%c2], %1";
return "vmov%?.<V_sz_elem>\t%P0[%c2], %1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr")]
@ -734,7 +734,7 @@
operands[0] = gen_rtx_REG (DImode, regno);
return "vmov%?.64\t%P0, %Q1, %R1";
return "vmov%?\t%P0, %Q1, %R1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_mcr_2_mcrr")]
@ -2555,126 +2555,65 @@
; Operand 3 (info word) is ignored because it does nothing useful with 64-bit
; elements.
(define_insn "neon_vget_lanedi"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VGET_LANE))]
(define_expand "neon_vget_lanedi"
[(match_operand:DI 0 "s_register_operand" "=r")
(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
neon_lane_bounds (operands[2], 0, 1);
return "vmov%?\t%Q0, %R0, %P1 @ di";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
emit_move_insn (operands[0], operands[1]);
DONE;
})
(define_insn "neon_vget_lanev2di"
[(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V2DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VGET_LANE))]
(define_expand "neon_vget_lanev2di"
[(match_operand:DI 0 "s_register_operand" "=r")
(match_operand:V2DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
rtx ops[2];
unsigned int regno = REGNO (operands[1]);
unsigned int elt = INTVAL (operands[2]);
neon_lane_bounds (operands[2], 0, 2);
emit_insn (gen_vec_extractv2di (operands[0], operands[1], operands[2]));
DONE;
})
ops[0] = operands[0];
ops[1] = gen_rtx_REG (DImode, regno + 2 * elt);
output_asm_insn ("vmov%?\t%Q0, %R0, %P1 @ v2di", ops);
return "";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vset_lane<mode>"
[(set (match_operand:VD 0 "s_register_operand" "=w")
(unspec:VD [(match_operand:<V_elem> 1 "s_register_operand" "r")
(match_operand:VD 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VSET_LANE))]
(define_expand "neon_vset_lane<mode>"
[(match_operand:VDQ 0 "s_register_operand" "=w")
(match_operand:<V_elem> 1 "s_register_operand" "r")
(match_operand:VDQ 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
unsigned int elt = INTVAL (operands[3]);
neon_lane_bounds (operands[3], 0, GET_MODE_NUNITS (<MODE>mode));
return "vmov%?.<V_sz_elem>\t%P0[%c3], %1";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
if (BYTES_BIG_ENDIAN)
{
unsigned int reg_nelts
= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode));
elt ^= reg_nelts - 1;
}
emit_insn (gen_vec_set<mode>_internal (operands[0], operands[1],
GEN_INT (1 << elt), operands[2]));
DONE;
})
; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored.
(define_insn "neon_vset_lanedi"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")
(match_operand:DI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VSET_LANE))]
(define_expand "neon_vset_lanedi"
[(match_operand:DI 0 "s_register_operand" "=w")
(match_operand:DI 1 "s_register_operand" "r")
(match_operand:DI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_NEON"
{
neon_lane_bounds (operands[3], 0, 1);
return "vmov%?\t%P0, %Q1, %R1 @ di";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vset_lane<mode>"
[(set (match_operand:VQ 0 "s_register_operand" "=w")
(unspec:VQ [(match_operand:<V_elem> 1 "s_register_operand" "r")
(match_operand:VQ 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VSET_LANE))]
"TARGET_NEON"
{
rtx ops[4];
unsigned int regno = REGNO (operands[0]);
unsigned int halfelts = GET_MODE_NUNITS (<MODE>mode) / 2;
unsigned int elt = INTVAL (operands[3]);
neon_lane_bounds (operands[3], 0, halfelts * 2);
ops[0] = gen_rtx_REG (<V_HALF>mode, regno + 2 * (elt / halfelts));
ops[1] = operands[1];
ops[2] = GEN_INT (elt % halfelts);
output_asm_insn ("vmov%?.<V_sz_elem>\t%P0[%c2], %1", ops);
return "";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vset_lanev2di"
[(set (match_operand:V2DI 0 "s_register_operand" "=w")
(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")
(match_operand:V2DI 2 "s_register_operand" "0")
(match_operand:SI 3 "immediate_operand" "i")]
UNSPEC_VSET_LANE))]
"TARGET_NEON"
{
rtx ops[2];
unsigned int regno = REGNO (operands[0]);
unsigned int elt = INTVAL (operands[3]);
neon_lane_bounds (operands[3], 0, 2);
ops[0] = gen_rtx_REG (DImode, regno + 2 * elt);
ops[1] = operands[1];
output_asm_insn ("vmov%?\t%P0, %Q1, %R1 @ v2di", ops);
return "";
}
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
)
emit_move_insn (operands[0], operands[1]);
DONE;
})
(define_expand "neon_vcreate<mode>"
[(match_operand:VDX 0 "s_register_operand" "")
@ -2688,8 +2627,7 @@
(define_insn "neon_vdup_n<mode>"
[(set (match_operand:VX 0 "s_register_operand" "=w")
(unspec:VX [(match_operand:<V_elem> 1 "s_register_operand" "r")]
UNSPEC_VDUP_N))]
(vec_duplicate:VX (match_operand:<V_elem> 1 "s_register_operand" "r")))]
"TARGET_NEON"
"vdup%?.<V_sz_elem>\t%<V_reg>0, %1"
;; Assume this schedules like vmov.
@ -2699,8 +2637,7 @@
(define_insn "neon_vdup_n<mode>"
[(set (match_operand:V32 0 "s_register_operand" "=w,w")
(unspec:V32 [(match_operand:<V_elem> 1 "s_register_operand" "r,t")]
UNSPEC_VDUP_N))]
(vec_duplicate:V32 (match_operand:<V_elem> 1 "s_register_operand" "r,t")))]
"TARGET_NEON"
"@
vdup%?.<V_sz_elem>\t%<V_reg>0, %1
@ -2710,61 +2647,76 @@
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vdup_ndi"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "r")]
UNSPEC_VDUP_N))]
(define_expand "neon_vdup_ndi"
[(match_operand:DI 0 "s_register_operand" "=w")
(match_operand:DI 1 "s_register_operand" "r")]
"TARGET_NEON"
"vmov%?\t%P0, %Q1, %R1"
[(set_attr "predicable" "yes")
(set_attr "neon_type" "neon_bp_simple")]
{
emit_move_insn (operands[0], operands[1]);
DONE;
}
)
(define_insn "neon_vdup_nv2di"
[(set (match_operand:V2DI 0 "s_register_operand" "=w")
(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "r")]
UNSPEC_VDUP_N))]
[(set (match_operand:V2DI 0 "s_register_operand" "=w,w")
(vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))]
"TARGET_NEON"
"vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1"
"@
vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1
vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1"
[(set_attr "predicable" "yes")
(set_attr "length" "8")
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vdup_lane<mode>"
[(set (match_operand:VD 0 "s_register_operand" "=w")
(unspec:VD [(match_operand:VD 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_VDUP_LANE))]
(define_insn "neon_vdup_lane<mode>_internal"
[(set (match_operand:VDQW 0 "s_register_operand" "=w")
(vec_duplicate:VDQW
(vec_select:<V_elem>
(match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
(parallel [(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_NEON"
{
neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<MODE>mode));
return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
if (BYTES_BIG_ENDIAN)
{
int elt = INTVAL (operands[2]);
elt = GET_MODE_NUNITS (<V_double_vector_mode>mode) - 1 - elt;
operands[2] = GEN_INT (elt);
}
if (<Is_d_reg>)
return "vdup.<V_sz_elem>\t%P0, %P1[%c2]";
else
return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
}
;; Assume this schedules like vmov.
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vdup_lane<mode>"
[(set (match_operand:VQ 0 "s_register_operand" "=w")
(unspec:VQ [(match_operand:<V_HALF> 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_VDUP_LANE))]
(define_expand "neon_vdup_lane<mode>"
[(match_operand:VDQW 0 "s_register_operand" "=w")
(match_operand:<V_double_vector_mode> 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
"TARGET_NEON"
{
neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_HALF>mode));
return "vdup.<V_sz_elem>\t%q0, %P1[%c2]";
}
;; Assume this schedules like vmov.
[(set_attr "neon_type" "neon_bp_simple")]
)
neon_lane_bounds (operands[2], 0, GET_MODE_NUNITS (<V_double_vector_mode>mode));
if (BYTES_BIG_ENDIAN)
{
unsigned int elt = INTVAL (operands[2]);
unsigned int reg_nelts
= 64 / GET_MODE_BITSIZE (GET_MODE_INNER (<V_double_vector_mode>mode));
elt ^= reg_nelts - 1;
operands[2] = GEN_INT (elt);
}
emit_insn (gen_neon_vdup_lane<mode>_internal (operands[0], operands[1],
operands[2]));
DONE;
})
; Scalar index is ignored, since only zero is valid here.
(define_expand "neon_vdup_lanedi"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(unspec:DI [(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_VDUP_LANE))]
[(match_operand:DI 0 "s_register_operand" "=w")
(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
"TARGET_NEON"
{
neon_lane_bounds (operands[2], 0, 1);
@ -2772,20 +2724,17 @@
DONE;
})
; Likewise.
(define_insn "neon_vdup_lanev2di"
[(set (match_operand:V2DI 0 "s_register_operand" "=w")
(unspec:V2DI [(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
UNSPEC_VDUP_LANE))]
; Likewise for v2di, as the DImode second operand has only a single element.
(define_expand "neon_vdup_lanev2di"
[(match_operand:V2DI 0 "s_register_operand" "=w")
(match_operand:DI 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
"TARGET_NEON"
{
neon_lane_bounds (operands[2], 0, 1);
return "vmov\t%e0, %P1\;vmov\t%f0, %P1";
}
[(set_attr "length" "8")
(set_attr "neon_type" "neon_bp_simple")]
)
emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1]));
DONE;
})
;; In this insn, operand 1 should be low, and operand 2 the high part of the
;; dest vector.
@ -2796,9 +2745,8 @@
(define_insn "neon_vcombine<mode>"
[(set (match_operand:<V_DOUBLE> 0 "s_register_operand" "=w")
(unspec:<V_DOUBLE> [(match_operand:VDX 1 "s_register_operand" "w")
(match_operand:VDX 2 "s_register_operand" "w")]
UNSPEC_VCOMBINE))]
(vec_concat:<V_DOUBLE> (match_operand:VDX 1 "s_register_operand" "w")
(match_operand:VDX 2 "s_register_operand" "w")))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
@ -2838,10 +2786,13 @@
(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_high<mode>"
[(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
(unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
UNSPEC_VGET_HIGH))]
(define_insn "neon_vget_highv16qi"
[(set (match_operand:V8QI 0 "s_register_operand" "=w")
(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
(parallel [(const_int 8) (const_int 9)
(const_int 10) (const_int 11)
(const_int 12) (const_int 13)
(const_int 14) (const_int 15)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
@ -2855,10 +2806,151 @@
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_low<mode>"
[(set (match_operand:<V_HALF> 0 "s_register_operand" "=w")
(unspec:<V_HALF> [(match_operand:VQX 1 "s_register_operand" "w")]
UNSPEC_VGET_LOW))]
(define_insn "neon_vget_highv8hi"
[(set (match_operand:V4HI 0 "s_register_operand" "=w")
(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
(parallel [(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src + 2)
return "vmov\t%P0, %f1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_highv4si"
[(set (match_operand:V2SI 0 "s_register_operand" "=w")
(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src + 2)
return "vmov\t%P0, %f1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_highv4sf"
[(set (match_operand:V2SF 0 "s_register_operand" "=w")
(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
(parallel [(const_int 2) (const_int 3)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src + 2)
return "vmov\t%P0, %f1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_highv2di"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
(parallel [(const_int 1)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src + 2)
return "vmov\t%P0, %f1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lowv16qi"
[(set (match_operand:V8QI 0 "s_register_operand" "=w")
(vec_select:V8QI (match_operand:V16QI 1 "s_register_operand" "w")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)
(const_int 4) (const_int 5)
(const_int 6) (const_int 7)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src)
return "vmov\t%P0, %e1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lowv8hi"
[(set (match_operand:V4HI 0 "s_register_operand" "=w")
(vec_select:V4HI (match_operand:V8HI 1 "s_register_operand" "w")
(parallel [(const_int 0) (const_int 1)
(const_int 2) (const_int 3)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src)
return "vmov\t%P0, %e1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lowv4si"
[(set (match_operand:V2SI 0 "s_register_operand" "=w")
(vec_select:V2SI (match_operand:V4SI 1 "s_register_operand" "w")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src)
return "vmov\t%P0, %e1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lowv4sf"
[(set (match_operand:V2SF 0 "s_register_operand" "=w")
(vec_select:V2SF (match_operand:V4SF 1 "s_register_operand" "w")
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);
int src = REGNO (operands[1]);
if (dest != src)
return "vmov\t%P0, %e1";
else
return "";
}
[(set_attr "neon_type" "neon_bp_simple")]
)
(define_insn "neon_vget_lowv2di"
[(set (match_operand:DI 0 "s_register_operand" "=w")
(vec_select:DI (match_operand:V2DI 1 "s_register_operand" "w")
(parallel [(const_int 0)])))]
"TARGET_NEON"
{
int dest = REGNO (operands[0]);

18
gcc/config/arm/neon.ml
View File

@ -967,7 +967,8 @@ let ops =
Use_operands [| Corereg; Dreg; Immed |],
"vget_lane", get_lane, pf_su_8_32;
Vget_lane,
[InfoWord;
[No_op;
InfoWord;
Disassembles_as [Use_operands [| Corereg; Corereg; Dreg |]];
Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
Use_operands [| Corereg; Dreg; Immed |],
@ -989,7 +990,8 @@ let ops =
Instruction_name ["vmov"]],
Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
set_lane, pf_su_8_32;
Vset_lane, [Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
Vset_lane, [No_op;
Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]];
Instruction_name ["vmov"]; Const_valuator (fun _ -> 0)],
Use_operands [| Dreg; Corereg; Dreg; Immed |], "vset_lane",
set_lane_notype, [S64; U64];
@ -1017,7 +1019,8 @@ let ops =
Use_operands [| Dreg; Corereg |], "vdup_n", bits_1,
pf_su_8_32;
Vdup_n,
[Instruction_name ["vmov"];
[No_op;
Instruction_name ["vmov"];
Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
Use_operands [| Dreg; Corereg |], "vdup_n", notype_1,
[S64; U64];
@ -1028,7 +1031,8 @@ let ops =
Use_operands [| Qreg; Corereg |], "vdupQ_n", bits_1,
pf_su_8_32;
Vdup_n,
[Instruction_name ["vmov"];
[No_op;
Instruction_name ["vmov"];
Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
Use_operands [| Dreg; Corereg; Corereg |]]],
Use_operands [| Qreg; Corereg |], "vdupQ_n", notype_1,
@ -1043,7 +1047,8 @@ let ops =
Use_operands [| Dreg; Corereg |],
"vmov_n", bits_1, pf_su_8_32;
Vmov_n,
[Builtin_name "vdup_n";
[No_op;
Builtin_name "vdup_n";
Instruction_name ["vmov"];
Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |]]],
Use_operands [| Dreg; Corereg |],
@ -1056,7 +1061,8 @@ let ops =
Use_operands [| Qreg; Corereg |],
"vmovQ_n", bits_1, pf_su_8_32;
Vmov_n,
[Builtin_name "vdupQ_n";
[No_op;
Builtin_name "vdupQ_n";
Instruction_name ["vmov"];
Disassembles_as [Use_operands [| Dreg; Corereg; Corereg |];
Use_operands [| Dreg; Corereg; Corereg |]]],

34
gcc/doc/arm-neon-intrinsics.texi
View File

@ -4750,13 +4750,11 @@
@itemize @bullet
@item uint64_t vget_lane_u64 (uint64x1_t, const int)
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
@end itemize
@itemize @bullet
@item int64_t vget_lane_s64 (int64x1_t, const int)
@*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
@end itemize
@ -4886,13 +4884,11 @@
@itemize @bullet
@item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@itemize @bullet
@item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@ -5081,13 +5077,11 @@
@itemize @bullet
@item uint64x1_t vdup_n_u64 (uint64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@itemize @bullet
@item int64x1_t vdup_n_s64 (int64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@ -5147,13 +5141,11 @@
@itemize @bullet
@item uint64x2_t vdupq_n_u64 (uint64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@itemize @bullet
@item int64x2_t vdupq_n_s64 (int64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@ -5213,13 +5205,11 @@
@itemize @bullet
@item uint64x1_t vmov_n_u64 (uint64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@itemize @bullet
@item int64x1_t vmov_n_s64 (int64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@ -5279,13 +5269,11 @@
@itemize @bullet
@item uint64x2_t vmovq_n_u64 (uint64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@itemize @bullet
@item int64x2_t vmovq_n_s64 (int64_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
@end itemize
@ -5571,18 +5559,6 @@
@end itemize
@itemize @bullet
@item uint64x1_t vget_low_u64 (uint64x2_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
@item int64x1_t vget_low_s64 (int64x2_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
@end itemize
@itemize @bullet
@item float32x2_t vget_low_f32 (float32x4_t)
@*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
@ -5601,6 +5577,16 @@
@end itemize
@itemize @bullet
@item uint64x1_t vget_low_u64 (uint64x2_t)
@end itemize
@itemize @bullet
@item int64x1_t vget_low_s64 (int64x2_t)
@end itemize
@subsubsection Conversions

29
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,32 @@
2010-07-02 Sandra Loosemore <sandra@codesourcery.com>
* gcc.target/arm/neon/vdup_ns64.c: Regenerated.
* gcc.target/arm/neon/vdup_nu64.c: Regenerated.
* gcc.target/arm/neon/vdupQ_ns64.c: Regenerated.
* gcc.target/arm/neon/vdupQ_nu64.c: Regenerated.
* gcc.target/arm/neon/vmov_ns64.c: Regenerated.
* gcc.target/arm/neon/vmov_nu64.c: Regenerated.
* gcc.target/arm/neon/vmovQ_ns64.c: Regenerated.
* gcc.target/arm/neon/vmovQ_nu64.c: Regenerated.
* gcc.target/arm/neon/vget_lanes64.c: Regenerated.
* gcc.target/arm/neon/vget_laneu64.c: Regenerated.
* gcc.target/arm/neon/vset_lanes64.c: Regenerated.
* gcc.target/arm/neon/vset_laneu64.c: Regenerated.
* gcc.target/arm/neon-vdup_ns64.c: New.
* gcc.target/arm/neon-vdup_nu64.c: New.
* gcc.target/arm/neon-vdupQ_ns64.c: New.
* gcc.target/arm/neon-vdupQ_nu64.c: New.
* gcc.target/arm/neon-vdupQ_lanes64.c: New.
* gcc.target/arm/neon-vdupQ_laneu64.c: New.
* gcc.target/arm/neon-vmov_ns64.c: New.
* gcc.target/arm/neon-vmov_nu64.c: New.
* gcc.target/arm/neon-vmovQ_ns64.c: New.
* gcc.target/arm/neon-vmovQ_nu64.c: New.
* gcc.target/arm/neon-vget_lanes64.c: New.
* gcc.target/arm/neon-vget_laneu64.c: New.
* gcc.target/arm/neon-vset_lanes64.c: New.
* gcc.target/arm/neon-vset_laneu64.c: New.
2010-07-02 Richard Guenther <rguenther@suse.de>
* g++.dg/torture/20100702-1.C: New testcase.

22
gcc/testsuite/gcc.target/arm/neon-vdupQ_lanes64.c Normal file
View File

@ -0,0 +1,22 @@
/* Test the `vdupq_lanes64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x2_t out_int64x2_t = {0, 0};
int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
out_int64x2_t = vdupq_lane_s64 ((int64x1_t)arg0_int64_t, 0);
if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
abort();
if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
abort();
return 0;
}

22
gcc/testsuite/gcc.target/arm/neon-vdupQ_laneu64.c Normal file
View File

@ -0,0 +1,22 @@
/* Test the `vdupq_laneu64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x2_t out_uint64x2_t = {0, 0};
uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
out_uint64x2_t = vdupq_lane_u64 ((uint64x1_t)arg0_uint64_t, 0);
if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
abort();
if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
abort();
return 0;
}

22
gcc/testsuite/gcc.target/arm/neon-vdupQ_ns64.c Normal file
View File

@ -0,0 +1,22 @@
/* Test the `vdupq_ns64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x2_t out_int64x2_t = {0, 0};
int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
abort();
if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
abort();
return 0;
}

22
gcc/testsuite/gcc.target/arm/neon-vdupQ_nu64.c Normal file
View File

@ -0,0 +1,22 @@
/* Test the `vdupq_nu64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x2_t out_uint64x2_t = {0, 0};
uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
abort();
if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vdup_ns64.c Normal file
View File

@ -0,0 +1,20 @@
/* Test the `vdup_ns64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x1_t out_int64x1_t = 0;
int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
out_int64x1_t = vdup_n_s64 (arg0_int64_t);
if ((int64_t)out_int64x1_t != arg0_int64_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vdup_nu64.c Normal file
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@ -0,0 +1,20 @@
/* Test the `vdup_nu64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x1_t out_uint64x1_t = 0;
uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vget_lanes64.c Normal file
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@ -0,0 +1,20 @@
/* Test the `vget_lane_s64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64_t out_int64_t = 0;
int64x1_t arg0_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
if (out_int64_t != (int64_t)arg0_int64x1_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vget_laneu64.c Normal file
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@ -0,0 +1,20 @@
/* Test the `vget_lane_u64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64_t out_uint64_t = 0;
uint64x1_t arg0_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
if (out_uint64_t != (uint64_t)arg0_uint64x1_t)
abort();
return 0;
}

22
gcc/testsuite/gcc.target/arm/neon-vmovQ_ns64.c Normal file
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@ -0,0 +1,22 @@
/* Test the `vmovq_ns64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x2_t out_int64x2_t = {0, 0};
int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
if (vgetq_lane_s64 (out_int64x2_t, 0) != arg0_int64_t)
abort();
if (vgetq_lane_s64 (out_int64x2_t, 1) != arg0_int64_t)
abort();
return 0;
}

23
gcc/testsuite/gcc.target/arm/neon-vmovQ_nu64.c Normal file
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@ -0,0 +1,23 @@
/* Test the `vmovq_nu64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x2_t out_uint64x2_t = {0, 0};
uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
if (vgetq_lane_u64 (out_uint64x2_t, 0) != arg0_uint64_t)
abort();
if (vgetq_lane_u64 (out_uint64x2_t, 1) != arg0_uint64_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vmov_ns64.c Normal file
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@ -0,0 +1,20 @@
/* Test the `vmov_ns64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x1_t out_int64x1_t = 0;
int64_t arg0_int64_t = (int64_t) 0xdeadbeef;
out_int64x1_t = vmov_n_s64 (arg0_int64_t);
if ((int64_t)out_int64x1_t != arg0_int64_t)
abort();
return 0;
}

20
gcc/testsuite/gcc.target/arm/neon-vmov_nu64.c Normal file
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@ -0,0 +1,20 @@
/* Test the `vmov_nu64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x1_t out_uint64x1_t = 0;
uint64_t arg0_uint64_t = (uint64_t) 0xdeadbeef;
out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
abort();
return 0;
}

21
gcc/testsuite/gcc.target/arm/neon-vset_lanes64.c Normal file
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@ -0,0 +1,21 @@
/* Test the `vset_lane_s64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
int64x1_t out_int64x1_t = 0;
int64_t arg0_int64_t = 0xf00f00f00LL;
int64x1_t arg1_int64x1_t = (int64x1_t) 0xdeadbeefbadf00dLL;
out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
if ((int64_t)out_int64x1_t != arg0_int64_t)
abort();
return 0;
}

21
gcc/testsuite/gcc.target/arm/neon-vset_laneu64.c Normal file
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@ -0,0 +1,21 @@
/* Test the `vset_lane_s64' ARM Neon intrinsic. */
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
/* { dg-options "-O0" } */
/* { dg-add-options arm_neon } */
#include "arm_neon.h"
#include <stdlib.h>
int main (void)
{
uint64x1_t out_uint64x1_t = 0;
uint64_t arg0_uint64_t = 0xf00f00f00LL;
uint64x1_t arg1_uint64x1_t = (uint64x1_t) 0xdeadbeefbadf00dLL;
out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
if ((uint64_t)out_uint64x1_t != arg0_uint64_t)
abort();
return 0;
}

2
gcc/testsuite/gcc.target/arm/neon/vdupQ_ns64.c
View File

@ -16,6 +16,4 @@ void test_vdupQ_ns64 (void)
out_int64x2_t = vdupq_n_s64 (arg0_int64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vdupQ_nu64.c
View File

@ -16,6 +16,4 @@ void test_vdupQ_nu64 (void)
out_uint64x2_t = vdupq_n_u64 (arg0_uint64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vdup_ns64.c
View File

@ -16,5 +16,4 @@ void test_vdup_ns64 (void)
out_int64x1_t = vdup_n_s64 (arg0_int64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vdup_nu64.c
View File

@ -16,5 +16,4 @@ void test_vdup_nu64 (void)
out_uint64x1_t = vdup_n_u64 (arg0_uint64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vget_lanes64.c
View File

@ -16,5 +16,4 @@ void test_vget_lanes64 (void)
out_int64_t = vget_lane_s64 (arg0_int64x1_t, 0);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vget_laneu64.c
View File

@ -16,5 +16,4 @@ void test_vget_laneu64 (void)
out_uint64_t = vget_lane_u64 (arg0_uint64x1_t, 0);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[rR\]\[0-9\]+, \[rR\]\[0-9\]+, \[dD\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vmovQ_ns64.c
View File

@ -16,6 +16,4 @@ void test_vmovQ_ns64 (void)
out_int64x2_t = vmovq_n_s64 (arg0_int64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

2
gcc/testsuite/gcc.target/arm/neon/vmovQ_nu64.c
View File

@ -16,6 +16,4 @@ void test_vmovQ_nu64 (void)
out_uint64x2_t = vmovq_n_u64 (arg0_uint64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vmov_ns64.c
View File

@ -16,5 +16,4 @@ void test_vmov_ns64 (void)
out_int64x1_t = vmov_n_s64 (arg0_int64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vmov_nu64.c
View File

@ -16,5 +16,4 @@ void test_vmov_nu64 (void)
out_uint64x1_t = vmov_n_u64 (arg0_uint64_t);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vset_lanes64.c
View File

@ -17,5 +17,4 @@ void test_vset_lanes64 (void)
out_int64x1_t = vset_lane_s64 (arg0_int64_t, arg1_int64x1_t, 0);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */

1
gcc/testsuite/gcc.target/arm/neon/vset_laneu64.c
View File

@ -17,5 +17,4 @@ void test_vset_laneu64 (void)
out_uint64x1_t = vset_lane_u64 (arg0_uint64_t, arg1_uint64x1_t, 0);
}
/* { dg-final { scan-assembler "vmov\[ \]+\[dD\]\[0-9\]+, \[rR\]\[0-9\]+, \[rR\]\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
/* { dg-final { cleanup-saved-temps } } */