m32r.md: Use define_constants for unspec and unspec_volatile.
* config/m32r/m32r.md: Use define_constants for unspec and unspec_volatile. From-SVN: r75656
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@ -1,3 +1,8 @@
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2004-01-10 Kazu Hirata <kazu@cs.umass.edu>
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* config/m32r/m32r.md: Use define_constants for unspec and
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unspec_volatile.
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2004-01-10 Jan Hubicka <jh@suse.cz>
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2004-01-10 Jan Hubicka <jh@suse.cz>
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PR opt/11635
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PR opt/11635
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@ -19,13 +19,19 @@
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;; Boston, MA 02111-1307, USA.
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;; Boston, MA 02111-1307, USA.
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;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
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;; unspec usage
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;; 0 - blockage
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;; 1 - flush_icache
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;; 2 - load_sda_base
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;; 3 - setting carry in addx/subx instructions.
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;; UNSPEC_VOLATILE usage
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(define_constants
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[(UNSPECV_BLOCKAGE 0)
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(UNSPECV_FLUSH_ICACHE 1)])
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;; UNSPEC usage
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(define_constants
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[(UNSPEC_LOAD_SDA_BASE 2)
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(UNSPEC_SET_CBIT 3)
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(UNSPEC_PIC_LOAD_ADDR 4)
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(UNSPEC_GET_PC 5)])
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;; Insn type. Used to default other attribute values.
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;; Insn type. Used to default other attribute values.
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(define_attr "type"
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(define_attr "type"
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"int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
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"int2,int4,load2,load4,load8,store2,store4,store8,shift2,shift4,mul2,div4,uncond_branch,branch,call,multi,misc"
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@ -564,7 +570,7 @@
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(define_expand "movsi_sda"
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(define_expand "movsi_sda"
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[(set (match_dup 2)
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[(set (match_dup 2)
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(unspec [(const_int 0)] 2))
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(unspec [(const_int 0)] UNSPEC_LOAD_SDA_BASE))
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(set (match_operand:SI 0 "register_operand" "")
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(set (match_operand:SI 0 "register_operand" "")
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(lo_sum:SI (match_dup 2)
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(lo_sum:SI (match_dup 2)
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(match_operand:SI 1 "small_data_operand" "")))]
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(match_operand:SI 1 "small_data_operand" "")))]
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@ -579,7 +585,7 @@
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(define_insn "*load_sda_base"
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(define_insn "*load_sda_base"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(const_int 0)] 2))]
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(unspec:SI [(const_int 0)] UNSPEC_LOAD_SDA_BASE))]
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""
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""
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"ld24 %0,#_SDA_BASE_"
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"ld24 %0,#_SDA_BASE_"
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[(set_attr "type" "int4")
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[(set_attr "type" "int4")
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@ -921,13 +927,13 @@
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(plus:SI (match_dup 5)
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(plus:SI (match_dup 5)
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
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(parallel [(set (match_dup 6)
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(parallel [(set (match_dup 6)
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(plus:SI (match_dup 6)
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(plus:SI (match_dup 6)
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(plus:SI (match_dup 7)
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(plus:SI (match_dup 7)
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])]
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
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"
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"
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{
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{
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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@ -951,7 +957,7 @@
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(plus:SI (match_operand:SI 2 "register_operand" "r")
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(plus:SI (match_operand:SI 2 "register_operand" "r")
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))]
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
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""
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""
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"addx %0,%2"
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"addx %0,%2"
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[(set_attr "type" "int2")
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[(set_attr "type" "int2")
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@ -991,13 +997,13 @@
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(minus:SI (match_dup 5)
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(minus:SI (match_dup 5)
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])
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(parallel [(set (match_dup 6)
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(parallel [(set (match_dup 6)
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(minus:SI (match_dup 6)
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(minus:SI (match_dup 6)
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(minus:SI (match_dup 7)
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(minus:SI (match_dup 7)
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))])]
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))])]
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"
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"
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{
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{
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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operands[4] = operand_subword (operands[0], (WORDS_BIG_ENDIAN != 0), 0, DImode);
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@ -1012,7 +1018,7 @@
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(minus:SI (match_operand:SI 2 "register_operand" "r")
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(minus:SI (match_operand:SI 2 "register_operand" "r")
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(ne:SI (reg:CC 17) (const_int 0)))))
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(ne:SI (reg:CC 17) (const_int 0)))))
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(set (reg:CC 17)
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(set (reg:CC 17)
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(unspec:CC [(const_int 0)] 3))]
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(unspec:CC [(const_int 0)] UNSPEC_SET_CBIT))]
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""
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""
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"subx %0,%2"
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"subx %0,%2"
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[(set_attr "type" "int2")
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[(set_attr "type" "int2")
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@ -2494,14 +2500,15 @@
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;; all of memory. This blocks insns from being moved across this point.
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;; all of memory. This blocks insns from being moved across this point.
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(define_insn "blockage"
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(define_insn "blockage"
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[(unspec_volatile [(const_int 0)] 0)]
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[(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
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""
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""
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"")
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"")
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;; Special pattern to flush the icache.
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;; Special pattern to flush the icache.
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(define_insn "flush_icache"
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(define_insn "flush_icache"
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[(unspec_volatile [(match_operand 0 "memory_operand" "m")] 1)
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[(unspec_volatile [(match_operand 0 "memory_operand" "m")]
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UNSPECV_FLUSH_ICACHE)
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(match_operand 1 "" "")
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(match_operand 1 "" "")
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(clobber (reg:SI 17))]
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(clobber (reg:SI 17))]
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""
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""
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@ -2700,7 +2707,7 @@
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(define_insn "pic_load_addr"
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(define_insn "pic_load_addr"
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[(set (match_operand:SI 0 "register_operand" "=r")
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[(set (match_operand:SI 0 "register_operand" "=r")
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(unspec:SI [(match_operand 1 "" "")] 4))]
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(unspec:SI [(match_operand 1 "" "")] UNSPEC_PIC_LOAD_ADDR))]
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"flag_pic"
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"flag_pic"
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"ld24 %0,%#%1"
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"ld24 %0,%#%1"
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[(set_attr "type" "int4")])
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[(set_attr "type" "int4")])
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@ -2710,7 +2717,7 @@
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(define_insn "get_pc"
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(define_insn "get_pc"
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[(clobber (reg:SI 14))
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[(clobber (reg:SI 14))
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(set (match_operand 0 "register_operand" "=r")
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(set (match_operand 0 "register_operand" "=r")
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(unspec [(match_operand 1 "" "")] 5))
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(unspec [(match_operand 1 "" "")] UNSPEC_GET_PC))
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(use (match_operand:SI 2 "immediate_operand" ""))]
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(use (match_operand:SI 2 "immediate_operand" ""))]
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"flag_pic"
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"flag_pic"
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"*
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"*
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