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re PR target/70131 (PowerPC ISA 2.07 is inefficient at doint (float)(int)x.) 

[gcc]
2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70131
	* config/rs6000/rs6000.md (round32<mode>2_fprs): Do not do the
	optimization if we have direct move.
	(roundu32<mode>2_fprs): Likewise.

[gcc/testsuite]
2016-03-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/70131
	* gcc.target/powerpc/ppc-round2.c: New test.

From-SVN: r234155
This commit is contained in:
Michael Meissner 2016-03-12 00:10:54 +00:00 committed by Michael Meissner
parent 089d955fa0
commit a3f6d680ea
4 changed files with 62 additions and 6 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2016-03-11 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70131
* config/rs6000/rs6000.md (round32<mode>2_fprs): Do not do the
optimization if we have direct move.
(roundu32<mode>2_fprs): Likewise.
2016-03-11 Bernd Schmidt <bschmidt@redhat.com>
PR target/70123

14
gcc/config/rs6000/rs6000.md
View File

@ -5387,10 +5387,12 @@
xsrdpiz %x0,%x1"
[(set_attr "type" "fp")])
;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
;; load to properly sign extend the value, but at least doing a store, load
;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
;; if we have 32-bit memory ops
;; Opitmize converting SF/DFmode to signed SImode and back to SF/DFmode. This
;; optimization prevents on ISA 2.06 systems and earlier having to store the
;; value from the FPR/vector unit to the stack, load the value into a GPR, sign
;; extend it, store it back on the stack from the GPR, load it back into the
;; FP/vector unit to do the rounding. If we have direct move (ISA 2.07),
;; disable using store and load to sign/zero extend the value.
(define_insn_and_split "*round32<mode>2_fprs"
[(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
(float:SFDF
@ -5399,7 +5401,7 @@
(clobber (match_scratch:DI 3 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
&& can_create_pseudo_p ()"
&& !TARGET_DIRECT_MOVE && can_create_pseudo_p ()"
"#"
""
[(pc)]
@ -5431,7 +5433,7 @@
(clobber (match_scratch:DI 2 "=d"))
(clobber (match_scratch:DI 3 "=d"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
&& TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU && !TARGET_DIRECT_MOVE
&& can_create_pseudo_p ()"
"#"
""

5
gcc/testsuite/ChangeLog
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@ -1,3 +1,8 @@
2016-03-11 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/70131
* gcc.target/powerpc/ppc-round2.c: New test.
2016-03-11 Bernd Schmidt <bschmidt@redhat.com>
PR target/70123

42
gcc/testsuite/gcc.target/powerpc/ppc-round2.c Normal file
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@ -0,0 +1,42 @@
/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
/* { dg-require-effective-target powerpc_p8vector_ok } */
/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
/* { dg-options "-O2 -mcpu=power8" } */
/* { dg-final { scan-assembler-times "fcfid " 2 } } */
/* { dg-final { scan-assembler-times "fcfids " 2 } } */
/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
/* { dg-final { scan-assembler-times "mfvsrd " 4 } } */
/* { dg-final { scan-assembler-times "mtvsrwa " 2 } } */
/* { dg-final { scan-assembler-times "mtvsrwz " 2 } } */
/* { dg-final { scan-assembler-not "lwz" } } */
/* { dg-final { scan-assembler-not "lfiwax " } } */
/* { dg-final { scan-assembler-not "lfiwzx " } } */
/* { dg-final { scan-assembler-not "stw" } } */
/* { dg-final { scan-assembler-not "stfiwx " } } */
/* Make sure we don't have loads/stores to the GPR unit. */
double
round_double_int (double a)
{
return (double)(int)a;
}
float
round_float_int (float a)
{
return (float)(int)a;
}
double
round_double_uint (double a)
{
return (double)(unsigned int)a;
}
float
round_float_uint (float a)
{
return (float)(unsigned int)a;
}