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MIPS: Fix mode mismatch error between Loongson builtin arguments and insn

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operands.

gcc/

	* config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
	argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
	builtins to SImode and emit a zero-extend, if necessary.

From-SVN: r245243
This commit is contained in:
Toma Tabacu 2017-02-07 10:34:47 +00:00 committed by Toma Tabacu
parent d95c2fc7b3
commit a4166fe553
2 changed files with 24 additions and 0 deletions
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6
gcc/ChangeLog
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@ -1,3 +1,9 @@
2017-02-07 Toma Tabacu <toma.tabacu@imgtec.com>
* config/mips/mips.c (mips_expand_builtin_insn): Convert the QImode
argument of the pshufh, psllh, psllw, psrah, psraw, psrlh, psrlw
builtins to SImode and emit a zero-extend, if necessary.
2017-02-06 Palmer Dabbelt <palmer@dabbelt.com>
* docs/invoke.texi (RISC-V Options): Alphabetize.

18
gcc/config/mips/mips.c
View File

@ -16571,9 +16571,27 @@ mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
{
machine_mode imode;
int rangelo = 0, rangehi = 0, error_opno = 0;
rtx sireg;
switch (icode)
{
/* The third operand of these instructions is in SImode, so we need to
bring the corresponding builtin argument from QImode into SImode. */
case CODE_FOR_loongson_pshufh:
case CODE_FOR_loongson_psllh:
case CODE_FOR_loongson_psllw:
case CODE_FOR_loongson_psrah:
case CODE_FOR_loongson_psraw:
case CODE_FOR_loongson_psrlh:
case CODE_FOR_loongson_psrlw:
gcc_assert (has_target_p && nops == 3 && ops[2].mode == QImode);
sireg = gen_reg_rtx (SImode);
emit_insn (gen_zero_extendqisi2 (sireg,
force_reg (QImode, ops[2].value)));
ops[2].value = sireg;
ops[2].mode = SImode;
break;
case CODE_FOR_msa_addvi_b:
case CODE_FOR_msa_addvi_h:
case CODE_FOR_msa_addvi_w: