Simplify movqi, add more !TARGET_5200 cases
From-SVN: r12533
This commit is contained in:
Ian Lance Taylor
parent
4431168e14
commit
a418b6c5ae
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@ -946,8 +946,8 @@
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}")
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(define_insn "movqi"
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[(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
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(match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi,?*a,m"))]
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[(set (match_operand:QI 0 "general_operand" "=d,*a,m")
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(match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
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""
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"*
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{
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@ -970,106 +970,6 @@
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return \"\";
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}
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/* Moving a byte into an address register is not possible. */
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/* Use d0 as an intermediate, but don't clobber its contents. */
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if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
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{
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/* ??? For 2.5, don't allow this choice and use secondary reloads
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instead.
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See if the address register is used in the address. If it
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is, we have to generate a more complex sequence than those below. */
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CC_STATUS_INIT;
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if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
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operands[1], NULL_RTX))
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{
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/* See if the stack pointer is used in the address. If it isn't,
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we can push d0 or d1 (the insn can't use both of them) on
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the stack, perform our move into d0/d1, copy the byte from d0/1,
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and pop d0/1. */
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if (! reg_mentioned_p (stack_pointer_rtx, operands[1]))
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{
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if (! refers_to_regno_p (0, 1, operands[1], NULL_RTX))
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return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\";
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else
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return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\";
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}
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else
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{
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/* Otherwise, we know that d0 cannot be used in the address
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(since sp and one address register is). Assume that sp is
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being used as a base register and replace the address
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register that is our operand[0] with d0. */
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rtx reg_map[FIRST_PSEUDO_REGISTER];
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int i;
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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reg_map[i] = 0;
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reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0);
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operands[1] = copy_rtx (operands[1]);
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replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0);
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return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
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}
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}
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/* If the address of operand 1 uses d0, choose d1 as intermediate. */
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if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
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return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\";
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/* Otherwise d0 is usable.
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(An effective address on the 68k can't use two d-regs.) */
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else
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return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\";
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}
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/* Likewise for moving from an address reg. */
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if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
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{
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/* ??? For 2.5, don't allow this choice and use secondary reloads
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instead.
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See if the address register is used in the address. If it
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is, we have to generate a more complex sequence than those below. */
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CC_STATUS_INIT;
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if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1,
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operands[0], NULL_RTX))
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{
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/* See if the stack pointer is used in the address. If it isn't,
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we can push d0 or d1 (the insn can't use both of them) on
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the stack, copy the byte to d0/1, perform our move from d0/d1,
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and pop d0/1. */
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if (! reg_mentioned_p (stack_pointer_rtx, operands[0]))
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{
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if (! refers_to_regno_p (0, 1, operands[0], NULL_RTX))
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return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\";
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else
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return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\";
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}
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else
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{
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/* Otherwise, we know that d0 cannot be used in the address
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(since sp and one address register is). Assume that sp is
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being used as a base register and replace the address
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register that is our operand[1] with d0. */
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rtx reg_map[FIRST_PSEUDO_REGISTER];
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int i;
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for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
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reg_map[i] = 0;
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reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0);
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operands[0] = copy_rtx (operands[0]);
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replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0);
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return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
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}
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}
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if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
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return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\";
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else
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return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\";
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}
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/* clr and st insns on 68000 read before writing.
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This isn't so on the 68010, but we have no TARGET_68010. */
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if (!ADDRESS_REG_P (operands[0])
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@ -2051,7 +1951,7 @@
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(const_int 32))
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(match_operand:DI 2 "general_operand" "0,0,0,0")))
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(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
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""
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"!TARGET_5200"
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"*
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{
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CC_STATUS_INIT;
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@ -2660,7 +2560,7 @@
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(ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
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(const_int 32))))
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(clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
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""
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"!TARGET_5200"
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"*
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{
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CC_STATUS_INIT;
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@ -3784,10 +3684,23 @@
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;; negation instructions
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(define_insn "negdi2"
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(define_expand "negdi2"
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[(set (match_operand:DI 0 "general_operand" "")
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(neg:DI (match_operand:DI 1 "general_operand" "")))]
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""
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"
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{
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if (TARGET_5200)
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emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
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else
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emit_insn (gen_negdi2_internal (operands[0], operands[1]));
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DONE;
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}")
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(define_insn "negdi2_internal"
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[(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
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(neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
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""
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"!TARGET_5200"
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"*
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{
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if (which_alternative == 0)
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@ -3802,6 +3715,21 @@
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return \"neg%.l %1\;negx%.l %0\";
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} ")
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(define_insn "negdi2_5200"
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[(set (match_operand:DI 0 "general_operand" "=<,do")
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(neg:DI (match_operand:DI 1 "general_operand" "0,0")))]
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"TARGET_5200"
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"*
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{
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if (which_alternative == 0)
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return \"neg%.l %0\;negx%.l %0\";
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if (GET_CODE (operands[0]) == REG)
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operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else
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operands[1] = adj_offsettable_operand (operands[0], 4);
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return \"neg%.l %1\;negx%.l %0\";
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} ")
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(define_insn "negsi2"
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[(set (match_operand:SI 0 "general_operand" "=dm")
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(neg:SI (match_operand:SI 1 "general_operand" "0")))]
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@ -4411,7 +4339,7 @@
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[(set (match_operand:DI 0 "general_operand" "")
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(ashiftrt:DI (match_operand:DI 1 "general_operand" "")
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(match_operand 2 "const_int_operand" "")))]
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""
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"!TARGET_5200"
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"
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{
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if (GET_CODE (operands[2]) != CONST_INT
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@ -4445,7 +4373,7 @@
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[(set (match_operand:HI 0 "register_operand" "=d")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
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(match_operand:HI 2 "general_operand" "dI")))]
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""
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"!TARGET_5200"
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"asr%.w %2,%0")
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(define_insn ""
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