expmed.c (emit_store_flag_1): New function.
* expmed.c (emit_store_flag_1): New function. (emit_store_flag): Call it. If we can't find a suitable scc insn, try a cstore insn. * expr.c (do_store_flag): If we can't find a scc insn, try cstore. Use do_compare_rtx_and_jump. * arm.h (BRANCH_COST): Increase to 2 on Thumb. * arm.md (cstoresi4): New define_expand. (cstoresi_eq0_thumb, cstoresi_ne0_thumb): Likewise. (cstoresi_eq0_thumb_insn, cstore_ne0_thumb_insn): New patterns. (cstoresi_nltu_thumb, thumb_addsi3_addgeu): New patterns. From-SVN: r118829
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
75dc0b383d
commit
a41a56b62d
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@ -1,3 +1,16 @@
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2006-11-14 Richard Earnshaw <rearnsha@arm.com>
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* expmed.c (emit_store_flag_1): New function.
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(emit_store_flag): Call it. If we can't find a suitable scc insn,
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try a cstore insn.
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* expr.c (do_store_flag): If we can't find a scc insn, try cstore.
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Use do_compare_rtx_and_jump.
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* arm.h (BRANCH_COST): Increase to 2 on Thumb.
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* arm.md (cstoresi4): New define_expand.
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(cstoresi_eq0_thumb, cstoresi_ne0_thumb): Likewise.
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(cstoresi_eq0_thumb_insn, cstore_ne0_thumb_insn): New patterns.
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(cstoresi_nltu_thumb, thumb_addsi3_addgeu): New patterns.
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2006-11-14 Caroline Tice <ctice@apple.com>
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* dwarf2out.c (debug_pubtypes_section): New static global variable.
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@ -2091,7 +2091,7 @@ do { \
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/* Try to generate sequences that don't involve branches, we can then use
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conditional instructions */
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#define BRANCH_COST \
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(TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
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(TARGET_ARM ? 4 : (optimize > 0 ? 2 : 0))
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/* Position Independent Code. */
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/* We decide which register to use based on the compilation options and
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@ -7460,6 +7460,198 @@
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(set_attr "length" "8")]
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)
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(define_expand "cstoresi4"
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[(set (match_operand:SI 0 "s_register_operand" "")
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(match_operator:SI 1 "arm_comparison_operator"
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[(match_operand:SI 2 "s_register_operand" "")
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(match_operand:SI 3 "reg_or_int_operand" "")]))]
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"TARGET_THUMB"
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"{
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rtx op3, scratch, scratch2;
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if (operands[3] == const0_rtx)
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{
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switch (GET_CODE (operands[1]))
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{
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case EQ:
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emit_insn (gen_cstoresi_eq0_thumb (operands[0], operands[2]));
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break;
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case NE:
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emit_insn (gen_cstoresi_ne0_thumb (operands[0], operands[2]));
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break;
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case LE:
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scratch = expand_binop (SImode, add_optab, operands[2], constm1_rtx,
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NULL_RTX, 0, OPTAB_WIDEN);
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scratch = expand_binop (SImode, ior_optab, operands[2], scratch,
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NULL_RTX, 0, OPTAB_WIDEN);
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expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
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operands[0], 1, OPTAB_WIDEN);
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break;
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case GE:
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scratch = expand_unop (SImode, one_cmpl_optab, operands[2],
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NULL_RTX, 1);
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expand_binop (SImode, lshr_optab, scratch, GEN_INT (31),
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NULL_RTX, 1, OPTAB_WIDEN);
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break;
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case GT:
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scratch = expand_binop (SImode, ashr_optab, operands[2],
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GEN_INT (31), NULL_RTX, 0, OPTAB_WIDEN);
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scratch = expand_binop (SImode, sub_optab, scratch, operands[2],
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NULL_RTX, 0, OPTAB_WIDEN);
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expand_binop (SImode, lshr_optab, scratch, GEN_INT (31), operands[0],
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0, OPTAB_WIDEN);
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break;
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/* LT is handled by generic code. No need for unsigned with 0. */
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default:
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FAIL;
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}
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DONE;
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}
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switch (GET_CODE (operands[1]))
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{
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case EQ:
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scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
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NULL_RTX, 0, OPTAB_WIDEN);
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emit_insn (gen_cstoresi_eq0_thumb (operands[0], scratch));
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break;
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case NE:
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scratch = expand_binop (SImode, sub_optab, operands[2], operands[3],
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NULL_RTX, 0, OPTAB_WIDEN);
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emit_insn (gen_cstoresi_ne0_thumb (operands[0], scratch));
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break;
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case LE:
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op3 = force_reg (SImode, operands[3]);
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scratch = expand_binop (SImode, lshr_optab, operands[2], GEN_INT (31),
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NULL_RTX, 1, OPTAB_WIDEN);
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scratch2 = expand_binop (SImode, ashr_optab, op3, GEN_INT (31),
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NULL_RTX, 0, OPTAB_WIDEN);
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emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch2,
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op3, operands[2]));
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break;
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case GE:
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op3 = operands[3];
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if (!thumb_cmp_operand (op3, SImode))
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op3 = force_reg (SImode, op3);
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scratch = expand_binop (SImode, ashr_optab, operands[2], GEN_INT (31),
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NULL_RTX, 0, OPTAB_WIDEN);
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scratch2 = expand_binop (SImode, lshr_optab, op3, GEN_INT (31),
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NULL_RTX, 1, OPTAB_WIDEN);
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emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch2,
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operands[2], op3));
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break;
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case LEU:
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op3 = force_reg (SImode, operands[3]);
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scratch = force_reg (SImode, const0_rtx);
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emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch,
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op3, operands[2]));
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break;
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case GEU:
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op3 = operands[3];
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if (!thumb_cmp_operand (op3, SImode))
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op3 = force_reg (SImode, op3);
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scratch = force_reg (SImode, const0_rtx);
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emit_insn (gen_thumb_addsi3_addgeu (operands[0], scratch, scratch,
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operands[2], op3));
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break;
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case LTU:
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op3 = operands[3];
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if (!thumb_cmp_operand (op3, SImode))
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op3 = force_reg (SImode, op3);
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scratch = gen_reg_rtx (SImode);
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emit_insn (gen_cstoresi_nltu_thumb (scratch, operands[2], op3));
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emit_insn (gen_negsi2 (operands[0], scratch));
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break;
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case GTU:
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op3 = force_reg (SImode, operands[3]);
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scratch = gen_reg_rtx (SImode);
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emit_insn (gen_cstoresi_nltu_thumb (scratch, op3, operands[2]));
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emit_insn (gen_negsi2 (operands[0], scratch));
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break;
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/* No good sequences for GT, LT. */
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default:
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FAIL;
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}
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DONE;
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}")
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(define_expand "cstoresi_eq0_thumb"
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[(parallel
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[(set (match_operand:SI 0 "s_register_operand" "")
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(eq:SI (match_operand:SI 1 "s_register_operand" "")
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(const_int 0)))
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(clobber (match_dup:SI 2))])]
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"TARGET_THUMB"
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"operands[2] = gen_reg_rtx (SImode);"
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)
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(define_expand "cstoresi_ne0_thumb"
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[(parallel
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[(set (match_operand:SI 0 "s_register_operand" "")
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(ne:SI (match_operand:SI 1 "s_register_operand" "")
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(const_int 0)))
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(clobber (match_dup:SI 2))])]
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"TARGET_THUMB"
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"operands[2] = gen_reg_rtx (SImode);"
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)
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(define_insn "*cstoresi_eq0_thumb_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=&l,l")
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(eq:SI (match_operand:SI 1 "s_register_operand" "l,0")
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(const_int 0)))
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(clobber (match_operand:SI 2 "s_register_operand" "=X,l"))]
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"TARGET_THUMB"
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"@
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neg\\t%0, %1\;adc\\t%0, %0, %1
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neg\\t%2, %1\;adc\\t%0, %1, %2"
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[(set_attr "length" "4")]
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)
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(define_insn "*cstoresi_ne0_thumb_insn"
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[(set (match_operand:SI 0 "s_register_operand" "=l")
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(ne:SI (match_operand:SI 1 "s_register_operand" "0")
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(const_int 0)))
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(clobber (match_operand:SI 2 "s_register_operand" "=l"))]
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"TARGET_THUMB"
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"sub\\t%2, %1, #1\;sbc\\t%0, %1, %2"
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[(set_attr "length" "4")]
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)
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(define_insn "cstoresi_nltu_thumb"
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[(set (match_operand:SI 0 "s_register_operand" "=l,l")
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(neg:SI (gtu:SI (match_operand:SI 1 "s_register_operand" "l,*h")
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(match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r"))))]
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"TARGET_THUMB"
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"cmp\\t%1, %2\;sbc\\t%0, %0, %0"
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[(set_attr "length" "4")]
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)
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;; Used as part of the expansion of thumb les sequence.
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(define_insn "thumb_addsi3_addgeu"
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[(set (match_operand:SI 0 "s_register_operand" "=l")
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(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "s_register_operand" "l"))
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(geu:SI (match_operand:SI 3 "s_register_operand" "l")
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(match_operand:SI 4 "thumb_cmp_operand" "lI"))))]
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"TARGET_THUMB"
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"cmp\\t%3, %4\;adc\\t%0, %1, %2"
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[(set_attr "length" "4")]
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)
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;; Conditional move insns
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193
gcc/expmed.c
193
gcc/expmed.c
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@ -5091,6 +5091,77 @@ expand_and (enum machine_mode mode, rtx op0, rtx op1, rtx target)
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return target;
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}
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/* Helper function for emit_store_flag. */
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static rtx
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emit_store_flag_1 (rtx target, rtx subtarget, enum machine_mode mode,
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int normalizep)
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{
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rtx op0;
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enum machine_mode target_mode = GET_MODE (target);
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/* If we are converting to a wider mode, first convert to
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TARGET_MODE, then normalize. This produces better combining
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opportunities on machines that have a SIGN_EXTRACT when we are
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testing a single bit. This mostly benefits the 68k.
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If STORE_FLAG_VALUE does not have the sign bit set when
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interpreted in MODE, we can do this conversion as unsigned, which
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is usually more efficient. */
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if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (mode))
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{
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convert_move (target, subtarget,
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(GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
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&& 0 == (STORE_FLAG_VALUE
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& ((HOST_WIDE_INT) 1
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<< (GET_MODE_BITSIZE (mode) -1))));
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op0 = target;
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mode = target_mode;
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}
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else
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op0 = subtarget;
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/* If we want to keep subexpressions around, don't reuse our last
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target. */
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if (optimize)
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subtarget = 0;
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/* Now normalize to the proper value in MODE. Sometimes we don't
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have to do anything. */
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if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
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;
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/* STORE_FLAG_VALUE might be the most negative number, so write
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the comparison this way to avoid a compiler-time warning. */
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else if (- normalizep == STORE_FLAG_VALUE)
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op0 = expand_unop (mode, neg_optab, op0, subtarget, 0);
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/* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
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it hard to use a value of just the sign bit due to ANSI integer
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constant typing rules. */
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else if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
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&& (STORE_FLAG_VALUE
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& ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))))
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op0 = expand_shift (RSHIFT_EXPR, mode, op0,
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size_int (GET_MODE_BITSIZE (mode) - 1), subtarget,
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normalizep == 1);
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else
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{
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gcc_assert (STORE_FLAG_VALUE & 1);
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op0 = expand_and (mode, op0, const1_rtx, subtarget);
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if (normalizep == -1)
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op0 = expand_unop (mode, neg_optab, op0, op0, 0);
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}
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/* If we were converting to a smaller mode, do the conversion now. */
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if (target_mode != mode)
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{
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convert_move (target, op0, 0);
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return target;
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}
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else
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return op0;
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}
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/* Emit a store-flags instruction for comparison CODE on OP0 and OP1
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and storing in TARGET. Normally return TARGET.
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Return 0 if that cannot be done.
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@ -5180,12 +5251,14 @@ emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
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{
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rtx op00, op01, op0both;
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/* Do a logical OR or AND of the two words and compare the result. */
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/* Do a logical OR or AND of the two words and compare the
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result. */
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op00 = simplify_gen_subreg (word_mode, op0, mode, 0);
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op01 = simplify_gen_subreg (word_mode, op0, mode, UNITS_PER_WORD);
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op0both = expand_binop (word_mode,
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op1 == const0_rtx ? ior_optab : and_optab,
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op00, op01, NULL_RTX, unsignedp, OPTAB_DIRECT);
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op00, op01, NULL_RTX, unsignedp,
|
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OPTAB_DIRECT);
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|
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if (op0both != 0)
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return emit_store_flag (target, code, op0both, op1, word_mode,
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|
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@ -5197,15 +5270,13 @@ emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
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|
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/* If testing the sign bit, can just test on high word. */
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op0h = simplify_gen_subreg (word_mode, op0, mode,
|
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subreg_highpart_offset (word_mode, mode));
|
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subreg_highpart_offset (word_mode,
|
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mode));
|
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return emit_store_flag (target, code, op0h, op1, word_mode,
|
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unsignedp, normalizep);
|
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}
|
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}
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|
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/* From now on, we won't change CODE, so set ICODE now. */
|
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icode = setcc_gen_code[(int) code];
|
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|
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/* If this is A < 0 or A >= 0, we can do this by taking the ones
|
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complement of A (for GE) and shifting the sign bit to the low bit. */
|
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if (op1 == const0_rtx && (code == LT || code == GE)
|
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|
|
@ -5213,7 +5284,8 @@ emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
|
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&& (normalizep || STORE_FLAG_VALUE == 1
|
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|| (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
|
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&& ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
|
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== (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1)))))
|
||||
== ((unsigned HOST_WIDE_INT) 1
|
||||
<< (GET_MODE_BITSIZE (mode) - 1))))))
|
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{
|
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subtarget = target;
|
||||
|
||||
|
|
@ -5248,6 +5320,8 @@ emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
|
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return op0;
|
||||
}
|
||||
|
||||
icode = setcc_gen_code[(int) code];
|
||||
|
||||
if (icode != CODE_FOR_nothing)
|
||||
{
|
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insn_operand_predicate_fn pred;
|
||||
|
|
@ -5305,72 +5379,65 @@ emit_store_flag (rtx target, enum rtx_code code, rtx op0, rtx op1,
|
|||
if (pattern)
|
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{
|
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emit_insn (pattern);
|
||||
return emit_store_flag_1 (target, subtarget, compare_mode,
|
||||
normalizep);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* We don't have an scc insn, so try a cstore insn. */
|
||||
|
||||
/* If we are converting to a wider mode, first convert to
|
||||
TARGET_MODE, then normalize. This produces better combining
|
||||
opportunities on machines that have a SIGN_EXTRACT when we are
|
||||
testing a single bit. This mostly benefits the 68k.
|
||||
for (compare_mode = mode; compare_mode != VOIDmode;
|
||||
compare_mode = GET_MODE_WIDER_MODE (compare_mode))
|
||||
{
|
||||
icode = cstore_optab->handlers[(int) compare_mode].insn_code;
|
||||
if (icode != CODE_FOR_nothing)
|
||||
break;
|
||||
}
|
||||
|
||||
If STORE_FLAG_VALUE does not have the sign bit set when
|
||||
interpreted in COMPARE_MODE, we can do this conversion as
|
||||
unsigned, which is usually more efficient. */
|
||||
if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (compare_mode))
|
||||
if (icode != CODE_FOR_nothing)
|
||||
{
|
||||
enum machine_mode result_mode
|
||||
= insn_data[(int) icode].operand[0].mode;
|
||||
rtx cstore_op0 = op0;
|
||||
rtx cstore_op1 = op1;
|
||||
|
||||
do_pending_stack_adjust ();
|
||||
last = get_last_insn ();
|
||||
|
||||
if (compare_mode != mode)
|
||||
{
|
||||
convert_move (target, subtarget,
|
||||
(GET_MODE_BITSIZE (compare_mode)
|
||||
<= HOST_BITS_PER_WIDE_INT)
|
||||
&& 0 == (STORE_FLAG_VALUE
|
||||
& ((HOST_WIDE_INT) 1
|
||||
<< (GET_MODE_BITSIZE (compare_mode) -1))));
|
||||
op0 = target;
|
||||
compare_mode = target_mode;
|
||||
cstore_op0 = convert_modes (compare_mode, mode, cstore_op0,
|
||||
unsignedp);
|
||||
cstore_op1 = convert_modes (compare_mode, mode, cstore_op1,
|
||||
unsignedp);
|
||||
}
|
||||
else
|
||||
op0 = subtarget;
|
||||
|
||||
if (!insn_data[(int) icode].operand[2].predicate (cstore_op0,
|
||||
compare_mode))
|
||||
cstore_op0 = copy_to_mode_reg (compare_mode, cstore_op0);
|
||||
|
||||
/* If we want to keep subexpressions around, don't reuse our
|
||||
last target. */
|
||||
if (!insn_data[(int) icode].operand[3].predicate (cstore_op1,
|
||||
compare_mode))
|
||||
cstore_op1 = copy_to_mode_reg (compare_mode, cstore_op1);
|
||||
|
||||
if (optimize)
|
||||
subtarget = 0;
|
||||
comparison = gen_rtx_fmt_ee (code, result_mode, cstore_op0,
|
||||
cstore_op1);
|
||||
subtarget = target;
|
||||
|
||||
/* Now normalize to the proper value in COMPARE_MODE. Sometimes
|
||||
we don't have to do anything. */
|
||||
if (normalizep == 0 || normalizep == STORE_FLAG_VALUE)
|
||||
;
|
||||
/* STORE_FLAG_VALUE might be the most negative number, so write
|
||||
the comparison this way to avoid a compiler-time warning. */
|
||||
else if (- normalizep == STORE_FLAG_VALUE)
|
||||
op0 = expand_unop (compare_mode, neg_optab, op0, subtarget, 0);
|
||||
if (optimize || !(insn_data[(int) icode].operand[0].predicate
|
||||
(subtarget, result_mode)))
|
||||
subtarget = gen_reg_rtx (result_mode);
|
||||
|
||||
/* We don't want to use STORE_FLAG_VALUE < 0 below since this
|
||||
makes it hard to use a value of just the sign bit due to
|
||||
ANSI integer constant typing rules. */
|
||||
else if (GET_MODE_BITSIZE (compare_mode) <= HOST_BITS_PER_WIDE_INT
|
||||
&& (STORE_FLAG_VALUE
|
||||
& ((HOST_WIDE_INT) 1
|
||||
<< (GET_MODE_BITSIZE (compare_mode) - 1))))
|
||||
op0 = expand_shift (RSHIFT_EXPR, compare_mode, op0,
|
||||
size_int (GET_MODE_BITSIZE (compare_mode) - 1),
|
||||
subtarget, normalizep == 1);
|
||||
else
|
||||
pattern = GEN_FCN (icode) (subtarget, comparison, cstore_op0,
|
||||
cstore_op1);
|
||||
|
||||
if (pattern)
|
||||
{
|
||||
gcc_assert (STORE_FLAG_VALUE & 1);
|
||||
|
||||
op0 = expand_and (compare_mode, op0, const1_rtx, subtarget);
|
||||
if (normalizep == -1)
|
||||
op0 = expand_unop (compare_mode, neg_optab, op0, op0, 0);
|
||||
emit_insn (pattern);
|
||||
return emit_store_flag_1 (target, subtarget, result_mode,
|
||||
normalizep);
|
||||
}
|
||||
|
||||
/* If we were converting to a smaller mode, do the
|
||||
conversion now. */
|
||||
if (target_mode != compare_mode)
|
||||
{
|
||||
convert_move (target, op0, 0);
|
||||
return target;
|
||||
}
|
||||
else
|
||||
return op0;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
32
gcc/expr.c
32
gcc/expr.c
|
|
@ -9155,6 +9155,17 @@ do_store_flag (tree exp, rtx target, enum machine_mode mode, int only_cheap)
|
|||
return 0;
|
||||
|
||||
icode = setcc_gen_code[(int) code];
|
||||
|
||||
if (icode == CODE_FOR_nothing)
|
||||
{
|
||||
enum machine_mode wmode;
|
||||
|
||||
for (wmode = operand_mode;
|
||||
icode == CODE_FOR_nothing && wmode != VOIDmode;
|
||||
wmode = GET_MODE_WIDER_MODE (wmode))
|
||||
icode = cstore_optab->handlers[(int) wmode].insn_code;
|
||||
}
|
||||
|
||||
if (icode == CODE_FOR_nothing
|
||||
|| (only_cheap && insn_data[(int) icode].operand[0].mode != mode))
|
||||
{
|
||||
|
|
@ -9200,25 +9211,10 @@ do_store_flag (tree exp, rtx target, enum machine_mode mode, int only_cheap)
|
|||
target = gen_reg_rtx (GET_MODE (target));
|
||||
|
||||
emit_move_insn (target, invert ? const0_rtx : const1_rtx);
|
||||
result = compare_from_rtx (op0, op1, code, unsignedp,
|
||||
operand_mode, NULL_RTX);
|
||||
if (GET_CODE (result) == CONST_INT)
|
||||
return (((result == const0_rtx && ! invert)
|
||||
|| (result != const0_rtx && invert))
|
||||
? const0_rtx : const1_rtx);
|
||||
|
||||
/* The code of RESULT may not match CODE if compare_from_rtx
|
||||
decided to swap its operands and reverse the original code.
|
||||
|
||||
We know that compare_from_rtx returns either a CONST_INT or
|
||||
a new comparison code, so it is safe to just extract the
|
||||
code from RESULT. */
|
||||
code = GET_CODE (result);
|
||||
|
||||
label = gen_label_rtx ();
|
||||
gcc_assert (bcc_gen_fctn[(int) code]);
|
||||
|
||||
emit_jump_insn ((*bcc_gen_fctn[(int) code]) (label));
|
||||
do_compare_rtx_and_jump (op0, op1, code, unsignedp, operand_mode, NULL_RTX,
|
||||
NULL_RTX, label);
|
||||
|
||||
emit_move_insn (target, invert ? const1_rtx : const0_rtx);
|
||||
emit_label (label);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue