mn10300.c: Include tm-constrs.h.
* config/mn10300/mn10300.c: Include tm-constrs.h. (struct liw_data): New data structure describing an LIW candidate instruction. (extract_bundle): Use struct liw_data. Allow small integer operands for some instructions. (check_liw_constraints): Use struct liw_data. Remove swapped parameter. Add comments describing the checks. Fix bug when assigning the source of liw1 to the source of liw2. (liw_candidate): Delete. Code moved into extract_bundle. (mn10300_bundle_liw): Use struct liw_data. Check constraints before swapping. * config/mn10300/predicates.md (liw_operand): New predicate. Allows registers and small integer constants. * config/mn10300/constraints.md (O): New constraint. Accetps integers in the range -8 to +7 inclusive. * config/mn10300/mn10300.md (movesi_internal): Add an alternative for moving a small integer into a register. Give this alternative LIW attributes. (addsi3, subsi3, cmpsi, lshrsi3, ashrsi3): Likewise. (ashlsi3): Likewise, plus give LIW attributes to the alternatives using the J,K,L and M constraints, (liw): Remove SI mode on second operands to allow for HI and QI mode values. (cmp_liw, liw_cmp): Likewise. Plus fix order of operands in the instruction. From-SVN: r170182
This commit is contained in:
Nick Clifton
Nick Clifton
parent
8a73faf108
commit
a45d420abf
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@ -1,3 +1,31 @@
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2011-02-15 Nick Clifton <nickc@redhat.com>
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* config/mn10300/mn10300.c: Include tm-constrs.h.
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(struct liw_data): New data structure describing an LIW candidate
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instruction.
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(extract_bundle): Use struct liw_data. Allow small integer
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operands for some instructions.
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(check_liw_constraints): Use struct liw_data. Remove swapped
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parameter. Add comments describing the checks. Fix bug when
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assigning the source of liw1 to the source of liw2.
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(liw_candidate): Delete. Code moved into extract_bundle.
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(mn10300_bundle_liw): Use struct liw_data. Check constraints
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before swapping.
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* config/mn10300/predicates.md (liw_operand): New predicate.
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Allows registers and small integer constants.
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* config/mn10300/constraints.md (O): New constraint. Accetps
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integers in the range -8 to +7 inclusive.
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* config/mn10300/mn10300.md (movesi_internal): Add an alternative
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for moving a small integer into a register. Give this alternative
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LIW attributes.
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(addsi3, subsi3, cmpsi, lshrsi3, ashrsi3): Likewise.
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(ashlsi3): Likewise, plus give LIW attributes to the alternatives
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using the J,K,L and M constraints,
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(liw): Remove SI mode on second operands to allow for HI and QI
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mode values.
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(cmp_liw, liw_cmp): Likewise. Plus fix order of operands in the
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instruction.
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2011-02-15 H.J. Lu <hongjiu.lu@intel.com>
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PR middle-end/47725
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@ -94,6 +94,12 @@
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(ior (match_test "ival == 255")
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(match_test "ival == 65535"))))
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(define_constraint "O"
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"An integer between -8 and +7 inclusive."
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(and (match_code "const_int")
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(and (match_test "ival >= -8")
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(match_test "ival <= 7"))))
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;; Floating-point constraints
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(define_constraint "G"
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"Floating-point zero."
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@ -40,6 +40,7 @@
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#include "obstack.h"
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#include "diagnostic-core.h"
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#include "tm_p.h"
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#include "tm-constrs.h"
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#include "target.h"
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#include "target-def.h"
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#include "df.h"
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@ -2945,91 +2946,143 @@ mn10300_split_and_operand_count (rtx op)
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}
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}
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/* Extract operands and (if requested) the LIW op type from the insn.
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Returns false if the insn can't be bundled. */
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struct liw_data
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{
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enum attr_liw slot;
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enum attr_liw_op op;
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rtx dest;
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rtx src;
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};
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/* Decide if the given insn is a candidate for LIW bundling. If it is then
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extract the operands and LIW attributes from the insn and use them to fill
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in the liw_data structure. Return true upon success or false if the insn
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cannot be bundled. */
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static bool
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extract_bundle (rtx insn, rtx * ops, enum attr_liw_op * plop)
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extract_bundle (rtx insn, struct liw_data * pdata)
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{
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enum attr_liw_op lop;
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rtx p, s;
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bool allow_consts = true;
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rtx p,s;
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gcc_assert (pdata != NULL);
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if (insn == NULL_RTX)
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return false;
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/* Make sure that we are dealing with a simple SET insn. */
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p = single_set (insn);
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s = SET_SRC (p);
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lop = get_attr_liw_op (insn);
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if (plop != NULL)
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* plop = lop;
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if (p == NULL_RTX)
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return false;
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switch (lop)
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/* Make sure that it could go into one of the LIW pipelines. */
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pdata->slot = get_attr_liw (insn);
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if (pdata->slot == LIW_BOTH)
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return false;
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pdata->op = get_attr_liw_op (insn);
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s = SET_SRC (p);
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switch (pdata->op)
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{
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case LIW_OP_MOV:
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ops[0] = SET_DEST (p);
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ops[1] = SET_SRC (p);
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pdata->dest = SET_DEST (p);
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pdata->src = SET_SRC (p);
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break;
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case LIW_OP_CMP:
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ops[0] = XEXP (SET_SRC (p), 0);
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ops[1] = XEXP (SET_SRC (p), 1);
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pdata->dest = XEXP (SET_SRC (p), 0);
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pdata->src = XEXP (SET_SRC (p), 1);
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break;
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case LIW_OP_NONE:
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return false;
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case LIW_OP_AND:
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case LIW_OP_OR:
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case LIW_OP_XOR:
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/* The AND, OR and XOR long instruction words only accept register arguments. */
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allow_consts = false;
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/* Fall through. */
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default:
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ops[0] = SET_DEST (p);
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ops[1] = XEXP (SET_SRC (p), 1);
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pdata->dest = SET_DEST (p);
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pdata->src = XEXP (SET_SRC (p), 1);
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break;
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}
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return REG_P (ops[0]) && REG_P (ops[1]);
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}
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/* Look for conflicts in the operands used in
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the potential bundling of the two insns. */
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static bool
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check_liw_constraints (rtx ops[4],
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enum attr_liw_op op1,
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enum attr_liw_op op2,
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bool swapped)
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{
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/* Look for the two destination registers being the same. This is OK if
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the first op is a comparison op, since it will compare the value prior
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to the completion of the second op. */
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if (REGNO (ops[0]) == REGNO (ops[2])
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&& ( (! swapped && op1 != LIW_OP_CMP)
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|| (swapped && op2 != LIW_OP_CMP)))
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if (! REG_P (pdata->dest))
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return false;
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/* Look for the source of the second op being the destination of the first op.
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Nomrally this will prevent the bundling since GCC has generated sequential
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operations and the LIW opcodes are executed in parallel. But if the first
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opcode is a MOV, we can copy its source to the second ops source. */
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if (swapped)
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return REGNO (ops[1]) != REGNO (ops[2]);
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if (REG_P (pdata->src))
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return true;
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if (REGNO (ops[3]) == REGNO (ops[0]))
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return allow_consts && satisfies_constraint_O (pdata->src);
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}
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/* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
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the instructions with the assumption that LIW1 would be executed before LIW2
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so we must check for overlaps between their sources and destinations. */
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static bool
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check_liw_constraints (struct liw_data * pliw1, struct liw_data * pliw2)
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{
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/* Check for slot conflicts. */
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if (pliw2->slot == pliw1->slot && pliw1->slot != LIW_EITHER)
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return false;
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/* If either operation is a compare, then "dest" is really an input; the real
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destination is CC_REG. So these instructions need different checks. */
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/* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
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check its values prior to any changes made by OP. */
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if (pliw1->op == LIW_OP_CMP)
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{
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if (op1 == LIW_OP_MOV)
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/* Two sequential comparisons means dead code, which ought to
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have been eliminated given that bundling only happens with
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optimization. We cannot bundle them in any case. */
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gcc_assert (pliw1->op != pliw2->op);
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return true;
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}
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/* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
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is the destination of OP, as the CMP will look at the old value, not the new
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one. */
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if (pliw2->op == LIW_OP_CMP)
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{
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if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
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return false;
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if (REG_P (pliw2->src))
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return REGNO (pliw2->src) != REGNO (pliw1->dest);
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return true;
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}
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/* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
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same destination register. */
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if (REGNO (pliw2->dest) == REGNO (pliw1->dest))
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return false;
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/* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
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of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
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we can replace the source in OP2 with the source of OP1. */
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if (REG_P (pliw2->src) && REGNO (pliw2->src) == REGNO (pliw1->dest))
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{
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if (pliw1->op == LIW_OP_MOV && REG_P (pliw1->src))
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{
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ops[3] = ops[1];
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if (! REG_P (pliw1->src)
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&& (pliw2->op == LIW_OP_AND
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|| pliw2->op == LIW_OP_OR
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|| pliw2->op == LIW_OP_XOR))
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return false;
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pliw2->src = pliw1->src;
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return true;
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}
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return false;
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}
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/* Everything else is OK. */
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return true;
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}
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/* Decide if the given insn is a candidate for LIW bundling. For now we just
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check that the insn has an LIW attribute. Later on we check operand
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constraints and such. */
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static bool
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liw_candidate (rtx insn)
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{
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return insn != NULL_RTX
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&& single_set (insn) != NULL_RTX
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&& get_attr_liw (insn) != LIW_BOTH;
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}
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/* Combine pairs of insns into LIW bundles. */
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static void
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@ -3039,61 +3092,41 @@ mn10300_bundle_liw (void)
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for (r = get_insns (); r != NULL_RTX; r = next_nonnote_nondebug_insn (r))
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{
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rtx insn1, insn2, ops[4];
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enum attr_liw liw1, liw2;
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enum attr_liw_op op1, op2;
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bool swapped = false;
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rtx insn1, insn2;
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struct liw_data liw1, liw2;
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insn1 = r;
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if (! liw_candidate (insn1))
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if (! extract_bundle (insn1, & liw1))
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continue;
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insn2 = next_nonnote_nondebug_insn (insn1);
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if (! liw_candidate (insn2))
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if (! extract_bundle (insn2, & liw2))
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continue;
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liw1 = get_attr_liw (insn1);
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if (liw1 == LIW_BOTH)
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continue;
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liw2 = get_attr_liw (insn2);
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if (liw2 == LIW_BOTH)
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continue;
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if (liw2 == liw1 && liw1 != LIW_EITHER)
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/* Check for source/destination overlap. */
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if (! check_liw_constraints (& liw1, & liw2))
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continue;
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/* The scheduler always groups the insns correctly, but not
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always in sequence. So, we can do a naive check and expect
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it to work. */
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if (liw1 == LIW_OP2 || liw2 == LIW_OP1)
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if (liw1.slot == LIW_OP2 || liw2.slot == LIW_OP1)
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{
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rtx r;
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enum attr_liw lt;
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r = insn1;
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insn1 = insn2;
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insn2 = r;
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lt = liw1;
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struct liw_data temp;
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temp = liw1;
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liw1 = liw2;
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liw2 = lt;
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swapped = true;
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liw2 = temp;
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}
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if (! extract_bundle (insn1, ops, & op1))
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continue;
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if (! extract_bundle (insn2, ops + 2, & op2))
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continue;
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if (! check_liw_constraints (ops, op1, op2, swapped))
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continue;
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delete_insn (insn2);
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if (op1 == LIW_OP_CMP)
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insn2 = gen_cmp_liw (ops[2], ops[3], ops[0], ops[1], GEN_INT (op2));
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else if (op2 == LIW_OP_CMP)
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insn2 = gen_liw_cmp (ops[0], ops[1], ops[2], ops[3], GEN_INT (op1));
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if (liw1.op == LIW_OP_CMP)
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insn2 = gen_cmp_liw (liw2.dest, liw2.src, liw1.dest, liw1.src,
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GEN_INT (liw2.op));
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else if (liw2.op == LIW_OP_CMP)
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insn2 = gen_liw_cmp (liw1.dest, liw1.src, liw2.dest, liw2.src,
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GEN_INT (liw1.op));
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else
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insn2 = gen_liw (ops[0], ops[2], ops[1], ops[3],
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GEN_INT (op1), GEN_INT (op2));
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insn2 = gen_liw (liw1.dest, liw2.dest, liw1.src, liw2.src,
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GEN_INT (liw1.op), GEN_INT (liw2.op));
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insn2 = emit_insn_after (insn2, insn1);
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delete_insn (insn1);
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|
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@ -419,9 +419,9 @@
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(define_insn "*movsi_internal"
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[(set (match_operand:SI 0 "nonimmediate_operand"
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"=r,r,r,m,r, A,*y,*y,*z,*d")
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"=r,r,r,r,m,r, A,*y,*y,*z,*d")
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(match_operand:SI 1 "general_operand"
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" 0,i,r,r,m,*y, A, i,*d,*z"))]
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" 0,O,i,r,r,m,*y, A, i,*d,*z"))]
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"register_operand (operands[0], SImode)
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|| register_operand (operands[1], SImode)"
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{
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@ -429,7 +429,8 @@
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{
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case 0:
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return "";
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case 1: /* imm-reg*/
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case 1: /* imm-reg. */
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case 2:
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/* See movhi for a discussion of sizes for 8-bit movu. Note that the
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24-bit movu is 6 bytes, which is the same size as the full 32-bit
|
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mov form for An and Dn. So again movu is only a win for Rn. */
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@ -443,24 +444,25 @@
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return "movu %1,%0";
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}
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/* FALLTHRU */
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case 2: /* reg-reg */
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case 3: /* reg-mem */
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case 4: /* mem-reg */
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case 5: /* sp-reg */
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case 6: /* reg-sp */
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case 7: /* imm-sp */
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case 8: /* reg-mdr */
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case 9: /* mdr-reg */
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case 3: /* reg-reg */
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case 4: /* reg-mem */
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case 5: /* mem-reg */
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case 6: /* sp-reg */
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case 7: /* reg-sp */
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case 8: /* imm-sp */
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case 9: /* reg-mdr */
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case 10: /* mdr-reg */
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return "mov %1,%0";
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default:
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gcc_unreachable ();
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}
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}
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[(set_attr "isa" "*,*,*,*,*,*,*,am33,*,*")
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(set_attr "liw" "*,*,either,*,*,*,*,*,*,*")
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[(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*")
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(set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*")
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(set_attr "liw_op" "mov")
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(set_attr_alternative "timings"
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[(const_int 11)
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(const_int 22)
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(const_int 22)
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(const_int 11)
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(if_then_else (eq_attr "cpu" "am34")
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|
|
@ -563,14 +565,14 @@
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;; ----------------------------------------------------------------------
|
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|
||||
(define_insn "addsi3"
|
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[(set (match_operand:SI 0 "register_operand" "=r,r,!*y,!r")
|
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0, 0, r")
|
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(match_operand:SI 2 "nonmemory_operand" "r,i, i, r")))
|
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r")
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(plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r")))
|
||||
(clobber (reg:CC CC_REG))]
|
||||
""
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||||
{ return mn10300_output_add (operands, false); }
|
||||
[(set_attr "timings" "11,11,11,22")
|
||||
(set_attr "liw" "either,*,*,*")
|
||||
[(set_attr "timings" "11,11,11,11,22")
|
||||
(set_attr "liw" "either,either,*,*,*")
|
||||
(set_attr "liw_op" "add")]
|
||||
)
|
||||
|
||||
|
|
@ -758,19 +760,20 @@
|
|||
;; ----------------------------------------------------------------------
|
||||
|
||||
(define_insn "subsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(minus:SI (match_operand:SI 1 "register_operand" "0,0,r")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,i,r")))
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
||||
(minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r")
|
||||
(match_operand:SI 2 "nonmemory_operand" "r,O,i,r")))
|
||||
(clobber (reg:CC CC_REG))]
|
||||
""
|
||||
"@
|
||||
sub %2,%0
|
||||
sub %2,%0
|
||||
sub %2,%0
|
||||
sub %2,%1,%0"
|
||||
[(set_attr "isa" "*,*,am33")
|
||||
(set_attr "liw" "either,*,*")
|
||||
[(set_attr "isa" "*,*,*,am33")
|
||||
(set_attr "liw" "either,either,*,*")
|
||||
(set_attr "liw_op" "sub")
|
||||
(set_attr "timings" "11,11,22")]
|
||||
(set_attr "timings" "11,11,11,22")]
|
||||
)
|
||||
|
||||
(define_insn "*subsi3_flags"
|
||||
|
|
@ -1374,8 +1377,8 @@
|
|||
|
||||
(define_insn "*cmpsi"
|
||||
[(set (reg CC_REG)
|
||||
(compare (match_operand:SI 0 "register_operand" "r,r")
|
||||
(match_operand:SI 1 "nonmemory_operand" "r,i")))]
|
||||
(compare (match_operand:SI 0 "register_operand" "r,r,r")
|
||||
(match_operand:SI 1 "nonmemory_operand" "r,O,i")))]
|
||||
"reload_completed"
|
||||
{
|
||||
/* The operands of CMP must be distinct registers. In the case where
|
||||
|
|
@ -1390,8 +1393,9 @@
|
|||
}
|
||||
[(set_attr_alternative "timings"
|
||||
[(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
|
||||
(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
|
||||
(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])
|
||||
(set_attr "liw" "either,*")
|
||||
(set_attr "liw" "either,either,*")
|
||||
(set_attr "liw_op" "cmp")]
|
||||
)
|
||||
|
||||
|
|
@ -1732,10 +1736,10 @@
|
|||
;; ----------------------------------------------------------------------
|
||||
|
||||
(define_insn "ashlsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,r")
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r")
|
||||
(ashift:SI
|
||||
(match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,i,r")))
|
||||
(match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r")))
|
||||
(clobber (reg:CC CC_REG))]
|
||||
""
|
||||
"@
|
||||
|
|
@ -1745,42 +1749,45 @@
|
|||
asl2 %0\;asl2 %0
|
||||
asl %S2,%0
|
||||
asl %S2,%0
|
||||
asl %S2,%0
|
||||
asl %2,%1,%0"
|
||||
[(set_attr "isa" "*,*,*,*,*,*,am33")
|
||||
(set_attr "liw" "*,*,*,*,op2,*,*")
|
||||
[(set_attr "isa" "*,*,*,*,*,*,*,am33")
|
||||
(set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*")
|
||||
(set_attr "liw_op" "asl")
|
||||
(set_attr "timings" "11,11,22,22,11,11,11")]
|
||||
(set_attr "timings" "11,11,22,22,11,11,11,11")]
|
||||
)
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=D,D,r")
|
||||
[(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" "D,i,r")))
|
||||
(match_operand:SI 1 "register_operand" "0,0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
|
||||
(clobber (reg:CC CC_REG))]
|
||||
""
|
||||
"@
|
||||
lsr %S2,%0
|
||||
lsr %S2,%0
|
||||
lsr %S2,%0
|
||||
lsr %2,%1,%0"
|
||||
[(set_attr "isa" "*,*,am33")
|
||||
(set_attr "liw" "op2,*,*")
|
||||
[(set_attr "isa" "*,*,*,am33")
|
||||
(set_attr "liw" "op2,op2,*,*")
|
||||
(set_attr "liw_op" "lsr")]
|
||||
)
|
||||
|
||||
(define_insn "ashrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=D,D,r")
|
||||
[(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" "D,i,r")))
|
||||
(match_operand:SI 1 "register_operand" "0,0,0,r")
|
||||
(match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
|
||||
(clobber (reg:CC CC_REG))]
|
||||
""
|
||||
"@
|
||||
asr %S2,%0
|
||||
asr %S2,%0
|
||||
asr %S2,%0
|
||||
asr %2,%1,%0"
|
||||
[(set_attr "isa" "*,*,am33")
|
||||
(set_attr "liw" "op2,*,*")
|
||||
[(set_attr "isa" "*,*,*,am33")
|
||||
(set_attr "liw" "op2,op2,*,*")
|
||||
(set_attr "liw_op" "asr")]
|
||||
)
|
||||
|
||||
|
|
@ -2100,12 +2107,12 @@
|
|||
(define_insn "liw"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(match_dup 0)
|
||||
(match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand 2 "liw_operand" "rO")
|
||||
(match_operand:SI 4 "const_int_operand" "")]
|
||||
UNSPEC_LIW))
|
||||
(set (match_operand:SI 1 "register_operand" "=r")
|
||||
(unspec:SI [(match_dup 1)
|
||||
(match_operand 3 "register_operand" "r")
|
||||
(match_operand 3 "liw_operand" "rO")
|
||||
(match_operand:SI 5 "const_int_operand" "")]
|
||||
UNSPEC_LIW))]
|
||||
"TARGET_ALLOW_LIW"
|
||||
|
|
@ -2119,14 +2126,14 @@
|
|||
(define_insn "cmp_liw"
|
||||
[(set (reg:CC CC_REG)
|
||||
(compare:CC (match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "register_operand" "r")))
|
||||
(match_operand 3 "liw_operand" "rO")))
|
||||
(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(match_dup 0)
|
||||
(match_operand 1 "register_operand" "r")
|
||||
(match_operand 1 "liw_operand" "rO")
|
||||
(match_operand:SI 4 "const_int_operand" "")]
|
||||
UNSPEC_LIW))]
|
||||
"TARGET_ALLOW_LIW"
|
||||
"cmp_%W4 %2, %3, %0, %1"
|
||||
"cmp_%W4 %3, %2, %1, %0"
|
||||
[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
|
||||
(const_int 13) (const_int 12)))]
|
||||
)
|
||||
|
|
@ -2134,14 +2141,14 @@
|
|||
(define_insn "liw_cmp"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r")
|
||||
(unspec:SI [(match_dup 0)
|
||||
(match_operand:SI 1 "register_operand" "r")
|
||||
(match_operand 1 "liw_operand" "rO")
|
||||
(match_operand:SI 4 "const_int_operand" "")]
|
||||
UNSPEC_LIW))
|
||||
(set (reg:CC CC_REG)
|
||||
(compare:CC (match_operand:SI 2 "register_operand" "r")
|
||||
(match_operand:SI 3 "register_operand" "r")))]
|
||||
(match_operand 3 "liw_operand" "rO")))]
|
||||
"TARGET_ALLOW_LIW"
|
||||
"%W4_cmp %0, %1, %2, %3"
|
||||
"%W4_cmp %1, %0, %3, %2"
|
||||
[(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
|
||||
(const_int 13) (const_int 12)))]
|
||||
)
|
||||
|
|
|
|||
|
|
@ -63,3 +63,7 @@
|
|||
|
||||
(define_predicate "CCZN_comparison_operator"
|
||||
(match_code "eq,ne,lt,ge"))
|
||||
|
||||
(define_predicate "liw_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_test "satisfies_constraint_O (op)")))
|
||||
|
|
|
|||
Loading…
Reference in New Issue