i386.md (sse_setccsf, [...]): New.
* i386.md (sse_setccsf, sse_setccdf): New. (sse_cmp* patterns): Use '%D' instead of outputtting condition flag directly. * i386.c (sse_comparison_operator): Accept the supported unordered comparses; be ready for fast_math. (print_operand): Support 'D'. From-SVN: r40131
This commit is contained in:
Jan Hubicka
Jan Hubicka
parent
91afe94118
commit
a46d1d38ae
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@ -1,3 +1,12 @@
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Wed Feb 28 19:05:37 CET 2001 Jan Hubicka <jh@suse.cz>
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* i386.md (sse_setccsf, sse_setccdf): New.
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(sse_cmp* patterns): Use '%D' instead of outputtting condition
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flag directly.
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* i386.c (sse_comparison_operator): Accept the supported unordered
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comparses; be ready for fast_math.
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(print_operand): Support 'D'.
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Wed Feb 28 18:54:51 CET 2001 Jan Hubicka <jh@suse.cz>
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* jump.c (reversed_comparison_code): Kill.
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@ -1318,7 +1318,29 @@ sse_comparison_operator (op, mode)
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enum machine_mode mode ATTRIBUTE_UNUSED;
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{
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enum rtx_code code = GET_CODE (op);
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return code == EQ || code == LT || code == LE || code == UNORDERED;
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switch (code)
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{
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/* Operations supported directly. */
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case EQ:
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case LT:
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case LE:
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case UNORDERED:
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case NE:
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case UNGE:
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case UNGT:
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case ORDERED:
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return 1;
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/* These are equivalent to ones above in non-IEEE comparisons. */
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case UNEQ:
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case UNLT:
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case UNLE:
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case LTGT:
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case GE:
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case GT:
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return !TARGET_IEEE_FP;
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default:
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return 0;
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}
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}
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/* Return 1 if OP is a valid comparison operator in valid mode. */
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int
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@ -3326,7 +3348,9 @@ print_reg (x, code, file)
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k -- likewise, print the SImode name of the register.
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h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
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y -- print "st(0)" instead of "st" as a register.
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m -- print "st(n)" as an mmx register. */
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m -- print "st(n)" as an mmx register.
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D -- print condition for SSE cmp instruction.
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*/
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void
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print_operand (file, x, code)
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@ -3460,6 +3484,47 @@ print_operand (file, x, code)
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}
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return;
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case 'D':
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/* Little bit of braindamage here. The SSE compare instructions
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does use completely different names for the comparisons that the
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fp conditional moves. */
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switch (GET_CODE (x))
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{
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case EQ:
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case UNEQ:
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fputs ("eq", file);
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break;
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case LT:
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case UNLT:
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fputs ("lt", file);
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break;
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case LE:
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case UNLE:
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fputs ("le", file);
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break;
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case UNORDERED:
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fputs ("unord", file);
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break;
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case NE:
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case LTGT:
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fputs ("neq", file);
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break;
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case UNGE:
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case GE:
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fputs ("nlt", file);
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break;
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case UNGT:
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case GT:
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fputs ("nle", file);
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break;
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case ORDERED:
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fputs ("ord", file);
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break;
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default:
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abort ();
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break;
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}
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return;
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case 'C':
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put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 0, 0, file);
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return;
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@ -9323,6 +9323,33 @@
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[(set_attr "type" "setcc")
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(set_attr "mode" "QI")])
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;; The SSE store flag instructions saves 0 or 0xffffffff to the result.
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;; subsequent logical operations are used to imitate conditional moves.
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;; 0xffffffff is NaN, but not in normalized form, so we can't represent
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;; it directly. Futher holding this value in pseudo register might bring
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;; problem in implicit normalization in spill code.
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;; So we don't define FLOAT_STORE_FLAG_VALUE and create these
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;; instructions after reload by splitting the conditional move patterns.
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(define_insn "*sse_setccsf"
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[(set (match_operand:SF 0 "register_operand" "=x")
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(match_operator:SF 1 "sse_comparison_operator"
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[(match_operand:SF 2 "register_operand" "0")
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(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
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"TARGET_SSE && reload_completed"
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"cmp%D1ss\\t{%3, %0|%0, %3}"
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[(set_attr "type" "sse")
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(set_attr "mode" "SF")])
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(define_insn "*sse_setccdf"
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[(set (match_operand:DF 0 "register_operand" "=Y")
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(match_operator:DF 1 "sse_comparison_operator"
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[(match_operand:DF 2 "register_operand" "0")
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(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
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"TARGET_SSE2 && reload_completed"
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"cmp%D1sd\\t{%3, %0|%0, %3}"
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[(set_attr "type" "sse")
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(set_attr "mode" "DF")])
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;; Basic conditional jump instructions.
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;; We ignore the overflow flag for signed branch instructions.
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@ -14111,22 +14138,7 @@
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[(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "x")]))]
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"TARGET_SSE"
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"*
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{
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switch (GET_CODE (operands[3]))
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{
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case EQ:
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return \"cmpeqps\\t{%2, %0|%0, %2}\";
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case LT:
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return \"cmpltps\\t{%2, %0|%0, %2}\";
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case LE:
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return \"cmpleps\\t{%2, %0|%0, %2}\";
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case UNORDERED:
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return \"cmpunordps\\t{%2, %0|%0, %2}\";
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default:
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abort ();
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}
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}"
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"cmp%D3ps\\t{%2, %0|%0, %2}"
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[(set_attr "type" "sse")])
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(define_insn "maskncmpv4sf3"
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@ -14136,22 +14148,7 @@
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[(match_operand:V4SF 1 "register_operand" "0")
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(match_operand:V4SF 2 "nonimmediate_operand" "x")])))]
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"TARGET_SSE"
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"*
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{
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switch (GET_CODE (operands[3]))
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{
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case EQ:
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return \"cmpneqps\\t{%2, %0|%0, %2}\";
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case LT:
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return \"cmpnltps\\t{%2, %0|%0, %2}\";
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case LE:
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return \"cmpnleps\\t{%2, %0|%0, %2}\";
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case UNORDERED:
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return \"cmpordps\\t{%2, %0|%0, %2}\";
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default:
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abort ();
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}
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}"
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"cmpn%D3ps\\t{%2, %0|%0, %2}"
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[(set_attr "type" "sse")])
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(define_insn "vmmaskcmpv4sf3"
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@ -14163,22 +14160,7 @@
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(match_dup 1)
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(const_int 1)))]
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"TARGET_SSE"
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"*
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{
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switch (GET_CODE (operands[3]))
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{
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case EQ:
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return \"cmpeqss\\t{%2, %0|%0, %2}\";
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case LT:
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return \"cmpltss\\t{%2, %0|%0, %2}\";
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case LE:
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return \"cmpless\\t{%2, %0|%0, %2}\";
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case UNORDERED:
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return \"cmpunordss\\t{%2, %0|%0, %2}\";
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default:
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abort ();
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}
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}"
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"cmp%D3ss\\t{%2, %0|%0, %2}"
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[(set_attr "type" "sse")])
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(define_insn "vmmaskncmpv4sf3"
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@ -14191,22 +14173,7 @@
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(subreg:V4SI (match_dup 1) 0)
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(const_int 1)))]
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"TARGET_SSE"
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"*
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{
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switch (GET_CODE (operands[3]))
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{
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case EQ:
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return \"cmpneqss\\t{%2, %0|%0, %2}\";
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case LT:
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return \"cmpnltss\\t{%2, %0|%0, %2}\";
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case LE:
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return \"cmpnless\\t{%2, %0|%0, %2}\";
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case UNORDERED:
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return \"cmpordss\\t{%2, %0|%0, %2}\";
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default:
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abort ();
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}
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}"
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"cmp%D3ss\\t{%2, %0|%0, %2}"
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[(set_attr "type" "sse")])
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(define_insn "sse_comi"
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