arm.md (all peepholes for post-increment operations): Delete.
* arm.md (all peepholes for post-increment operations): Delete. (strqi_preinc, strqi_predec, loadqi_preinc, loadqi_predec) (loadqisi_preinc, loadqisi_predec, strsi_preinc, strsi_predec) (loadsi_preinc, loadsi_predec, strqi_shiftpreinc, strqi_shiftpredec) (loadqi_shiftpreinc, loadqi_shiftpredec, strsi_shiftpreinc) (strsishift_predec, loadsi_shiftpreinc, loadsi_shiftpredec): Delete. From-SVN: r102589
This commit is contained in:
parent
06581725b9
commit
a4ccc33614
|
@ -1,3 +1,12 @@
|
|||
2005-07-30 Richard Earnshaw <richard.earnshaw@arm.com>
|
||||
|
||||
* arm.md (all peepholes for post-increment operations): Delete.
|
||||
(strqi_preinc, strqi_predec, loadqi_preinc, loadqi_predec)
|
||||
(loadqisi_preinc, loadqisi_predec, strsi_preinc, strsi_predec)
|
||||
(loadsi_preinc, loadsi_predec, strqi_shiftpreinc, strqi_shiftpredec)
|
||||
(loadqi_shiftpreinc, loadqi_shiftpredec, strsi_shiftpreinc)
|
||||
(strsishift_predec, loadsi_shiftpreinc, loadsi_shiftpredec): Delete.
|
||||
|
||||
2005-07-30 James A. Morrison <phython@gcc.gnu.org>
|
||||
|
||||
* fold-const.c (tree_expr_nonnegative_p): Always return true for
|
||||
|
|
|
@ -9405,396 +9405,6 @@
|
|||
(set_attr "type" "load1")]
|
||||
)
|
||||
|
||||
;; the arm can support extended pre-inc instructions
|
||||
|
||||
;; In all these cases, we use operands 0 and 1 for the register being
|
||||
;; incremented because those are the operands that local-alloc will
|
||||
;; tie and these are the pair most likely to be tieable (and the ones
|
||||
;; that will benefit the most).
|
||||
|
||||
;; We reject the frame pointer if it occurs anywhere in these patterns since
|
||||
;; elimination will cause too many headaches.
|
||||
|
||||
(define_insn "*strqi_preinc"
|
||||
[(set (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
|
||||
(match_operand:SI 2 "index_operand" "rJ")))
|
||||
(match_operand:QI 3 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"str%?b\\t%3, [%0, %2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strqi_predec"
|
||||
[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operand:SI 2 "s_register_operand" "r")))
|
||||
(match_operand:QI 3 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"str%?b\\t%3, [%0, -%2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqi_preinc"
|
||||
[(set (match_operand:QI 3 "s_register_operand" "=r")
|
||||
(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
|
||||
(match_operand:SI 2 "index_operand" "rJ"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?b\\t%3, [%0, %2]!"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqi_predec"
|
||||
[(set (match_operand:QI 3 "s_register_operand" "=r")
|
||||
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operand:SI 2 "s_register_operand" "r"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?b\\t%3, [%0, -%2]!"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqisi_preinc"
|
||||
[(set (match_operand:SI 3 "s_register_operand" "=r")
|
||||
(zero_extend:SI
|
||||
(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
|
||||
(match_operand:SI 2 "index_operand" "rJ")))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?b\\t%3, [%0, %2]!\\t%@ z_extendqisi"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqisi_predec"
|
||||
[(set (match_operand:SI 3 "s_register_operand" "=r")
|
||||
(zero_extend:SI
|
||||
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operand:SI 2 "s_register_operand" "r")))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?b\\t%3, [%0, -%2]!\\t%@ z_extendqisi"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strsi_preinc"
|
||||
[(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
|
||||
(match_operand:SI 2 "index_operand" "rJ")))
|
||||
(match_operand:SI 3 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"str%?\\t%3, [%0, %2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strsi_predec"
|
||||
[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operand:SI 2 "s_register_operand" "r")))
|
||||
(match_operand:SI 3 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"str%?\\t%3, [%0, -%2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadsi_preinc"
|
||||
[(set (match_operand:SI 3 "s_register_operand" "=r")
|
||||
(mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
|
||||
(match_operand:SI 2 "index_operand" "rJ"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?\\t%3, [%0, %2]!"
|
||||
[(set_attr "type" "load1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadsi_predec"
|
||||
[(set (match_operand:SI 3 "s_register_operand" "=r")
|
||||
(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operand:SI 2 "s_register_operand" "r"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[2])"
|
||||
"ldr%?\\t%3, [%0, -%2]!"
|
||||
[(set_attr "type" "load1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strqi_shiftpreinc"
|
||||
[(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])
|
||||
(match_operand:SI 1 "s_register_operand" "0")))
|
||||
(match_operand:QI 5 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
|
||||
(match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"str%?b\\t%5, [%0, %3%S2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strqi_shiftpredec"
|
||||
[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])))
|
||||
(match_operand:QI 5 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"str%?b\\t%5, [%0, -%3%S2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqi_shiftpreinc"
|
||||
[(set (match_operand:QI 5 "s_register_operand" "=r")
|
||||
(mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])
|
||||
(match_operand:SI 1 "s_register_operand" "0"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
|
||||
(match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"ldr%?b\\t%5, [%0, %3%S2]!"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadqi_shiftpredec"
|
||||
[(set (match_operand:QI 5 "s_register_operand" "=r")
|
||||
(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")]))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"ldr%?b\\t%5, [%0, -%3%S2]!"
|
||||
[(set_attr "type" "load_byte")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strsi_shiftpreinc"
|
||||
[(set (mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])
|
||||
(match_operand:SI 1 "s_register_operand" "0")))
|
||||
(match_operand:SI 5 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
|
||||
(match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"str%?\\t%5, [%0, %3%S2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*strsi_shiftpredec"
|
||||
[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])))
|
||||
(match_operand:SI 5 "s_register_operand" "r"))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"str%?\\t%5, [%0, -%3%S2]!"
|
||||
[(set_attr "type" "store1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadsi_shiftpreinc"
|
||||
[(set (match_operand:SI 5 "s_register_operand" "=r")
|
||||
(mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")])
|
||||
(match_operand:SI 1 "s_register_operand" "0"))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
|
||||
(match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"ldr%?\\t%5, [%0, %3%S2]!"
|
||||
[(set_attr "type" "load1")
|
||||
(set_attr "predicable" "yes")]
|
||||
)
|
||||
|
||||
(define_insn "*loadsi_shiftpredec"
|
||||
[(set (match_operand:SI 5 "s_register_operand" "=r")
|
||||
(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
|
||||
(match_operator:SI 2 "shift_operator"
|
||||
[(match_operand:SI 3 "s_register_operand" "r")
|
||||
(match_operand:SI 4 "const_shift_operand" "n")]))))
|
||||
(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
|
||||
(match_dup 4)])))]
|
||||
"TARGET_ARM
|
||||
&& !arm_eliminable_register (operands[0])
|
||||
&& !arm_eliminable_register (operands[1])
|
||||
&& !arm_eliminable_register (operands[3])"
|
||||
"ldr%?\\t%5, [%0, -%3%S2]!"
|
||||
[(set_attr "type" "load1")
|
||||
(set_attr "predicable" "yes")])
|
||||
|
||||
; It can also support extended post-inc expressions, but combine doesn't
|
||||
; try these....
|
||||
; It doesn't seem worth adding peepholes for anything but the most common
|
||||
; cases since, unlike combine, the increment must immediately follow the load
|
||||
; for this pattern to match.
|
||||
; We must watch to see that the source/destination register isn't also the
|
||||
; same as the base address register, and that if the index is a register,
|
||||
; that it is not the same as the base address register. In such cases the
|
||||
; instruction that we would generate would have UNPREDICTABLE behavior so
|
||||
; we cannot use it.
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
|
||||
(match_operand:QI 2 "s_register_operand" "r"))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[2]) != REGNO (operands[0]))
|
||||
&& (GET_CODE (operands[1]) != REG
|
||||
|| (REGNO (operands[1]) != REGNO (operands[0])))"
|
||||
"str%?b\\t%2, [%0], %1"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:QI 0 "s_register_operand" "=r")
|
||||
(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
|
||||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& REGNO (operands[0]) != REGNO(operands[1])
|
||||
&& (GET_CODE (operands[2]) != REG
|
||||
|| REGNO(operands[0]) != REGNO (operands[2]))"
|
||||
"ldr%?b\\t%0, [%1], %2"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "+r"))
|
||||
(match_operand:SI 2 "s_register_operand" "r"))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[2]) != REGNO (operands[0]))
|
||||
&& (GET_CODE (operands[1]) != REG
|
||||
|| (REGNO (operands[1]) != REGNO (operands[0])))"
|
||||
"str%?\\t%2, [%0], %1"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(mem:SI (match_operand:SI 1 "s_register_operand" "+r")))
|
||||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& REGNO (operands[0]) != REGNO(operands[1])
|
||||
&& (GET_CODE (operands[2]) != REG
|
||||
|| REGNO(operands[0]) != REGNO (operands[2]))"
|
||||
"ldr%?\\t%0, [%1], %2"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:SI (match_operand:SI 0 "s_register_operand" "+r")
|
||||
(match_operand:SI 1 "index_operand" "rJ")))
|
||||
(match_operand:QI 2 "s_register_operand" "r"))
|
||||
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[2]) != REGNO (operands[0]))
|
||||
&& (GET_CODE (operands[1]) != REG
|
||||
|| (REGNO (operands[1]) != REGNO (operands[0])))"
|
||||
"str%?b\\t%2, [%0, %1]!"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:SI (match_operator:SI 4 "shift_operator"
|
||||
[(match_operand:SI 0 "s_register_operand" "r")
|
||||
(match_operand:SI 1 "const_int_operand" "n")])
|
||||
(match_operand:SI 2 "s_register_operand" "+r")))
|
||||
(match_operand:QI 3 "s_register_operand" "r"))
|
||||
(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
|
||||
(match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[3]) != REGNO (operands[2]))
|
||||
&& (REGNO (operands[0]) != REGNO (operands[2]))"
|
||||
"str%?b\\t%3, [%2, %0%S4]!"
|
||||
)
|
||||
|
||||
; This pattern is never tried by combine, so do it as a peephole
|
||||
|
||||
(define_peephole2
|
||||
|
|
Loading…
Reference in New Issue