arm.md (all peepholes for post-increment operations): Delete.
* arm.md (all peepholes for post-increment operations): Delete. (strqi_preinc, strqi_predec, loadqi_preinc, loadqi_predec) (loadqisi_preinc, loadqisi_predec, strsi_preinc, strsi_predec) (loadsi_preinc, loadsi_predec, strqi_shiftpreinc, strqi_shiftpredec) (loadqi_shiftpreinc, loadqi_shiftpredec, strsi_shiftpreinc) (strsishift_predec, loadsi_shiftpreinc, loadsi_shiftpredec): Delete. From-SVN: r102589
This commit is contained in:
Richard Earnshaw
Richard Earnshaw
parent
06581725b9
commit
a4ccc33614
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@ -1,3 +1,12 @@
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2005-07-30 Richard Earnshaw <richard.earnshaw@arm.com>
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* arm.md (all peepholes for post-increment operations): Delete.
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(strqi_preinc, strqi_predec, loadqi_preinc, loadqi_predec)
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(loadqisi_preinc, loadqisi_predec, strsi_preinc, strsi_predec)
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(loadsi_preinc, loadsi_predec, strqi_shiftpreinc, strqi_shiftpredec)
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(loadqi_shiftpreinc, loadqi_shiftpredec, strsi_shiftpreinc)
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(strsishift_predec, loadsi_shiftpreinc, loadsi_shiftpredec): Delete.
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2005-07-30 James A. Morrison <phython@gcc.gnu.org>
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* fold-const.c (tree_expr_nonnegative_p): Always return true for
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@ -9405,396 +9405,6 @@
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(set_attr "type" "load1")]
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)
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;; the arm can support extended pre-inc instructions
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;; In all these cases, we use operands 0 and 1 for the register being
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;; incremented because those are the operands that local-alloc will
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;; tie and these are the pair most likely to be tieable (and the ones
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;; that will benefit the most).
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;; We reject the frame pointer if it occurs anywhere in these patterns since
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;; elimination will cause too many headaches.
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(define_insn "*strqi_preinc"
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[(set (mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "index_operand" "rJ")))
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(match_operand:QI 3 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"str%?b\\t%3, [%0, %2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strqi_predec"
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[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operand:SI 2 "s_register_operand" "r")))
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(match_operand:QI 3 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"str%?b\\t%3, [%0, -%2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqi_preinc"
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[(set (match_operand:QI 3 "s_register_operand" "=r")
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(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "index_operand" "rJ"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?b\\t%3, [%0, %2]!"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqi_predec"
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[(set (match_operand:QI 3 "s_register_operand" "=r")
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(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operand:SI 2 "s_register_operand" "r"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?b\\t%3, [%0, -%2]!"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqisi_preinc"
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[(set (match_operand:SI 3 "s_register_operand" "=r")
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(zero_extend:SI
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(mem:QI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "index_operand" "rJ")))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?b\\t%3, [%0, %2]!\\t%@ z_extendqisi"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqisi_predec"
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[(set (match_operand:SI 3 "s_register_operand" "=r")
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(zero_extend:SI
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(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operand:SI 2 "s_register_operand" "r")))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?b\\t%3, [%0, -%2]!\\t%@ z_extendqisi"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strsi_preinc"
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[(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "index_operand" "rJ")))
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(match_operand:SI 3 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"str%?\\t%3, [%0, %2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strsi_predec"
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[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operand:SI 2 "s_register_operand" "r")))
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(match_operand:SI 3 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"str%?\\t%3, [%0, -%2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadsi_preinc"
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[(set (match_operand:SI 3 "s_register_operand" "=r")
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(mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
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(match_operand:SI 2 "index_operand" "rJ"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?\\t%3, [%0, %2]!"
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[(set_attr "type" "load1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadsi_predec"
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[(set (match_operand:SI 3 "s_register_operand" "=r")
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(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operand:SI 2 "s_register_operand" "r"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_dup 2)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[2])"
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"ldr%?\\t%3, [%0, -%2]!"
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[(set_attr "type" "load1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strqi_shiftpreinc"
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[(set (mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])
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(match_operand:SI 1 "s_register_operand" "0")))
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(match_operand:QI 5 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"str%?b\\t%5, [%0, %3%S2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strqi_shiftpredec"
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[(set (mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])))
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(match_operand:QI 5 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"str%?b\\t%5, [%0, -%3%S2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqi_shiftpreinc"
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[(set (match_operand:QI 5 "s_register_operand" "=r")
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(mem:QI (plus:SI (match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])
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(match_operand:SI 1 "s_register_operand" "0"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"ldr%?b\\t%5, [%0, %3%S2]!"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadqi_shiftpredec"
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[(set (match_operand:QI 5 "s_register_operand" "=r")
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(mem:QI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")]))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"ldr%?b\\t%5, [%0, -%3%S2]!"
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[(set_attr "type" "load_byte")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strsi_shiftpreinc"
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[(set (mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])
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(match_operand:SI 1 "s_register_operand" "0")))
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(match_operand:SI 5 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"str%?\\t%5, [%0, %3%S2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*strsi_shiftpredec"
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[(set (mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])))
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(match_operand:SI 5 "s_register_operand" "r"))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"str%?\\t%5, [%0, -%3%S2]!"
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[(set_attr "type" "store1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadsi_shiftpreinc"
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[(set (match_operand:SI 5 "s_register_operand" "=r")
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(mem:SI (plus:SI (match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")])
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(match_operand:SI 1 "s_register_operand" "0"))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
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(match_dup 1)))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"ldr%?\\t%5, [%0, %3%S2]!"
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[(set_attr "type" "load1")
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(set_attr "predicable" "yes")]
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)
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(define_insn "*loadsi_shiftpredec"
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[(set (match_operand:SI 5 "s_register_operand" "=r")
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(mem:SI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
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(match_operator:SI 2 "shift_operator"
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[(match_operand:SI 3 "s_register_operand" "r")
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(match_operand:SI 4 "const_shift_operand" "n")]))))
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(set (match_operand:SI 0 "s_register_operand" "=r")
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(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
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(match_dup 4)])))]
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"TARGET_ARM
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&& !arm_eliminable_register (operands[0])
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&& !arm_eliminable_register (operands[1])
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&& !arm_eliminable_register (operands[3])"
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"ldr%?\\t%5, [%0, -%3%S2]!"
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[(set_attr "type" "load1")
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(set_attr "predicable" "yes")])
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; It can also support extended post-inc expressions, but combine doesn't
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; try these....
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; It doesn't seem worth adding peepholes for anything but the most common
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; cases since, unlike combine, the increment must immediately follow the load
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; for this pattern to match.
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; We must watch to see that the source/destination register isn't also the
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; same as the base address register, and that if the index is a register,
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; that it is not the same as the base address register. In such cases the
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; instruction that we would generate would have UNPREDICTABLE behavior so
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; we cannot use it.
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(define_peephole
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[(set (mem:QI (match_operand:SI 0 "s_register_operand" "+r"))
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(match_operand:QI 2 "s_register_operand" "r"))
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(set (match_dup 0)
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(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
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"TARGET_ARM
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&& (REGNO (operands[2]) != REGNO (operands[0]))
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&& (GET_CODE (operands[1]) != REG
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|| (REGNO (operands[1]) != REGNO (operands[0])))"
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"str%?b\\t%2, [%0], %1"
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)
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||||
|
||||
(define_peephole
|
||||
[(set (match_operand:QI 0 "s_register_operand" "=r")
|
||||
(mem:QI (match_operand:SI 1 "s_register_operand" "+r")))
|
||||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& REGNO (operands[0]) != REGNO(operands[1])
|
||||
&& (GET_CODE (operands[2]) != REG
|
||||
|| REGNO(operands[0]) != REGNO (operands[2]))"
|
||||
"ldr%?b\\t%0, [%1], %2"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:SI (match_operand:SI 0 "s_register_operand" "+r"))
|
||||
(match_operand:SI 2 "s_register_operand" "r"))
|
||||
(set (match_dup 0)
|
||||
(plus:SI (match_dup 0) (match_operand:SI 1 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[2]) != REGNO (operands[0]))
|
||||
&& (GET_CODE (operands[1]) != REG
|
||||
|| (REGNO (operands[1]) != REGNO (operands[0])))"
|
||||
"str%?\\t%2, [%0], %1"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (match_operand:SI 0 "s_register_operand" "=r")
|
||||
(mem:SI (match_operand:SI 1 "s_register_operand" "+r")))
|
||||
(set (match_dup 1)
|
||||
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
|
||||
"TARGET_ARM
|
||||
&& REGNO (operands[0]) != REGNO(operands[1])
|
||||
&& (GET_CODE (operands[2]) != REG
|
||||
|| REGNO(operands[0]) != REGNO (operands[2]))"
|
||||
"ldr%?\\t%0, [%1], %2"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:SI (match_operand:SI 0 "s_register_operand" "+r")
|
||||
(match_operand:SI 1 "index_operand" "rJ")))
|
||||
(match_operand:QI 2 "s_register_operand" "r"))
|
||||
(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[2]) != REGNO (operands[0]))
|
||||
&& (GET_CODE (operands[1]) != REG
|
||||
|| (REGNO (operands[1]) != REGNO (operands[0])))"
|
||||
"str%?b\\t%2, [%0, %1]!"
|
||||
)
|
||||
|
||||
(define_peephole
|
||||
[(set (mem:QI (plus:SI (match_operator:SI 4 "shift_operator"
|
||||
[(match_operand:SI 0 "s_register_operand" "r")
|
||||
(match_operand:SI 1 "const_int_operand" "n")])
|
||||
(match_operand:SI 2 "s_register_operand" "+r")))
|
||||
(match_operand:QI 3 "s_register_operand" "r"))
|
||||
(set (match_dup 2) (plus:SI (match_op_dup 4 [(match_dup 0) (match_dup 1)])
|
||||
(match_dup 2)))]
|
||||
"TARGET_ARM
|
||||
&& (REGNO (operands[3]) != REGNO (operands[2]))
|
||||
&& (REGNO (operands[0]) != REGNO (operands[2]))"
|
||||
"str%?b\\t%3, [%2, %0%S4]!"
|
||||
)
|
||||
|
||||
; This pattern is never tried by combine, so do it as a peephole
|
||||
|
||||
(define_peephole2
|
||||
|
|
|
|||
Loading…
Reference in New Issue