More consistent access to sparc %ger register.
* config/sparc/sparc.md (fpack16_vis, fpackfix_vis, fpack32_vis): Make GSR_REG an input operand to UNSPEC instead of a parallel USE. (faligndata<V64I:mode>_vis): Likewise and use DI mode. (alignaddrsi_vis, alignaddrdi_vis, alignaddrlsi_vis, alignaddrldi_vis): Reference GSR_REG in DI mode, simplify convoluted expressions by using zero_extract. (bshuffle<V64I:mode>_vis): Reference GSR_REG in DI mode. From-SVN: r179489
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@ -1,3 +1,13 @@
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2011-10-03 David S. Miller <davem@davemloft.net>
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* config/sparc/sparc.md (fpack16_vis, fpackfix_vis, fpack32_vis): Make
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GSR_REG an input operand to UNSPEC instead of a parallel USE.
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(faligndata<V64I:mode>_vis): Likewise and use DI mode.
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(alignaddrsi_vis, alignaddrdi_vis, alignaddrlsi_vis, alignaddrldi_vis):
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Reference GSR_REG in DI mode, simplify convoluted expressions by using
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zero_extract.
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(bshuffle<V64I:mode>_vis): Reference GSR_REG in DI mode.
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2011-10-03 Maxim Kuvyrkov <maxim@codesourcery.com>
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* tree-eh.c (remove_unreachable_handlers): Obvious cleanup.
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@ -7867,9 +7867,9 @@
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(define_insn "fpack16_vis"
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[(set (match_operand:V4QI 0 "register_operand" "=f")
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(unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")]
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UNSPEC_FPACK16))
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(use (reg:DI GSR_REG))]
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(unspec:V4QI [(match_operand:V4HI 1 "register_operand" "e")
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(reg:DI GSR_REG)]
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UNSPEC_FPACK16))]
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"TARGET_VIS"
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"fpack16\t%1, %0"
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[(set_attr "type" "fga")
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@ -7877,9 +7877,9 @@
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(define_insn "fpackfix_vis"
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[(set (match_operand:V2HI 0 "register_operand" "=f")
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(unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")]
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UNSPEC_FPACKFIX))
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(use (reg:DI GSR_REG))]
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(unspec:V2HI [(match_operand:V2SI 1 "register_operand" "e")
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(reg:DI GSR_REG)]
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UNSPEC_FPACKFIX))]
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"TARGET_VIS"
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"fpackfix\t%1, %0"
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[(set_attr "type" "fga")
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@ -7888,9 +7888,9 @@
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(define_insn "fpack32_vis"
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[(set (match_operand:V8QI 0 "register_operand" "=e")
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(unspec:V8QI [(match_operand:V2SI 1 "register_operand" "e")
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(match_operand:V8QI 2 "register_operand" "e")]
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UNSPEC_FPACK32))
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(use (reg:DI GSR_REG))]
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(match_operand:V8QI 2 "register_operand" "e")
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(reg:DI GSR_REG)]
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UNSPEC_FPACK32))]
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"TARGET_VIS"
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"fpack32\t%1, %2, %0"
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[(set_attr "type" "fga")
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@ -8053,9 +8053,9 @@
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(define_insn "faligndata<V64I:mode>_vis"
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[(set (match_operand:V64I 0 "register_operand" "=e")
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(unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
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(match_operand:V64I 2 "register_operand" "e")]
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UNSPEC_ALIGNDATA))
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(use (reg:SI GSR_REG))]
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(match_operand:V64I 2 "register_operand" "e")
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(reg:DI GSR_REG)]
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UNSPEC_ALIGNDATA))]
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"TARGET_VIS"
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"faligndata\t%1, %2, %0"
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[(set_attr "type" "fga")
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@ -8065,10 +8065,8 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
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(match_operand:SI 2 "register_or_zero_operand" "rJ")))
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(set (reg:SI GSR_REG)
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(ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
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(and:SI (plus:SI (match_dup 1) (match_dup 2))
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(const_int 7))))]
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(set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
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(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
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"TARGET_VIS"
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"alignaddr\t%r1, %r2, %0")
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@ -8076,10 +8074,8 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
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(match_operand:DI 2 "register_or_zero_operand" "rJ")))
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(set (reg:SI GSR_REG)
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(ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
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(and:SI (truncate:SI (plus:DI (match_dup 1) (match_dup 2)))
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(const_int 7))))]
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(set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
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(plus:DI (match_dup 1) (match_dup 2)))]
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"TARGET_VIS"
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"alignaddr\t%r1, %r2, %0")
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@ -8087,11 +8083,9 @@
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[(set (match_operand:SI 0 "register_operand" "=r")
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(plus:SI (match_operand:SI 1 "register_or_zero_operand" "rJ")
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(match_operand:SI 2 "register_or_zero_operand" "rJ")))
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(set (reg:SI GSR_REG)
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(ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
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(xor:SI (and:SI (plus:SI (match_dup 1) (match_dup 2))
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(const_int 7))
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(const_int 7))))]
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(set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
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(xor:DI (zero_extend:DI (plus:SI (match_dup 1) (match_dup 2)))
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(const_int 7)))]
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"TARGET_VIS"
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"alignaddrl\t%r1, %r2, %0")
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@ -8099,12 +8093,9 @@
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[(set (match_operand:DI 0 "register_operand" "=r")
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(plus:DI (match_operand:DI 1 "register_or_zero_operand" "rJ")
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(match_operand:DI 2 "register_or_zero_operand" "rJ")))
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(set (reg:SI GSR_REG)
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(ior:SI (and:SI (reg:SI GSR_REG) (const_int -8))
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(xor:SI (and:SI (truncate:SI (plus:DI (match_dup 1)
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(match_dup 2)))
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(const_int 7))
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(const_int 7))))]
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(set (zero_extract:DI (reg:DI GSR_REG) (const_int 3) (const_int 0))
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(xor:DI (plus:DI (match_dup 1) (match_dup 2))
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(const_int 7)))]
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"TARGET_VIS"
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"alignaddrl\t%r1, %r2, %0")
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@ -8252,7 +8243,7 @@
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[(set (match_operand:V64I 0 "register_operand" "=e")
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(unspec:V64I [(match_operand:V64I 1 "register_operand" "e")
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(match_operand:V64I 2 "register_operand" "e")
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(reg:SI GSR_REG)]
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(reg:DI GSR_REG)]
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UNSPEC_BSHUFFLE))]
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"TARGET_VIS2"
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"bshuffle\t%1, %2, %0"
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