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aarch64-simd.md (*aarch64_simd_ld1r<mode>): New. 

2013-01-14  Tejas Belagod  <tejas.belagod@arm.com>

gcc/
	* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
	* config/aarch64/iterators.md (VALLDI): New.

testsuite/
	* gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
	* gcc.target/aarch64/vect-ld1r-compile.c: New.
	* gcc.target/aarch64/vect-ld1r-fp.c: New.
	* gcc.target/aarch64/vect-ld1r.c: New.
	* gcc.target/aarch64/vect-ld1r.x: New.

From-SVN: r195158
This commit is contained in:
Tejas Belagod 2013-01-14 17:48:52 +00:00 committed by Tejas Belagod
parent e6f0e05240
commit a50344cbf3
9 changed files with 186 additions and 0 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2013-01-14 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64-simd.md (*aarch64_simd_ld1r<mode>): New.
* config/aarch64/iterators.md (VALLDI): New.
2012-01-14 Uros Bizjak <ubizjak@gmail.com>
Andi Kleen <ak@linux.intel.com>

8
gcc/config/aarch64/aarch64-simd.md
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@ -3559,3 +3559,11 @@
DONE;
})
(define_insn "*aarch64_simd_ld1r<mode>"
[(set (match_operand:VALLDI 0 "register_operand" "=w")
(vec_duplicate:VALLDI
(match_operand:<VEL> 1 "aarch64_simd_struct_operand" "Utv")))]
"TARGET_SIMD"
"ld1r\\t{%0.<Vtype>}, %1"
[(set_attr "simd_type" "simd_load1r")
(set_attr "simd_mode" "<MODE>")])

3
gcc/config/aarch64/iterators.md
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@ -89,6 +89,9 @@
;; All modes.
(define_mode_iterator VALL [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF])
;; All vector modes and DI.
(define_mode_iterator VALLDI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI V2SF V4SF V2DF DI])
;; Vector modes for Integer reduction across lanes.
(define_mode_iterator VDQV [V8QI V16QI V4HI V8HI V4SI])

8
gcc/testsuite/ChangeLog
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@ -1,3 +1,11 @@
2013-01-14 Tejas Belagod <tejas.belagod@arm.com>
* gcc.target/aarch64/aarch64/vect-ld1r-compile-fp.c: New.
* gcc.target/aarch64/vect-ld1r-compile.c: New.
* gcc.target/aarch64/vect-ld1r-fp.c: New.
* gcc.target/aarch64/vect-ld1r.c: New.
* gcc.target/aarch64/vect-ld1r.x: New.
2012-01-14 Andi Kleen <ak@linux.intel.com>
PR target/55948

13
gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile-fp.c Normal file
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@ -0,0 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fno-vect-cost-model" } */
#include "stdint.h"
#include "vect-ld1r.x"
DEF (float)
DEF (double)
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */

18
gcc/testsuite/gcc.target/aarch64/vect-ld1r-compile.c Normal file
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@ -0,0 +1,18 @@
/* { dg-do compile } */
/* { dg-options "-O3 -fno-vect-cost-model" } */
#include "stdint.h"
#include "vect-ld1r.x"
DEF (int8_t)
DEF (int16_t)
DEF (int32_t)
DEF (int64_t)
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8b"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.16b"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4h"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.8h"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.4s"} } */
/* { dg-final { scan-assembler "ldr\\t\x\[0-9\]+"} } */
/* { dg-final { scan-assembler "ld1r\\t\{v\[0-9\]+\.2d"} } */

51
gcc/testsuite/gcc.target/aarch64/vect-ld1r-fp.c Normal file
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@ -0,0 +1,51 @@
/* { dg-do run } */
/* { dg-options "-O3" } */
extern void abort (void);
#include "stdint.h"
#include "vect-ld1r.x"
DEF (float)
DEF (double)
#define FOOD(TYPE) \
foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
#define FOOQ(TYPE) \
foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
#define CHECKD(TYPE) \
for (i = 0; i < 8 / sizeof (TYPE); i++) \
if (output_ ## TYPE[i] != a_ ## TYPE) \
abort ()
#define CHECKQ(TYPE) \
for (i = 0; i < 32 / sizeof (TYPE); i++) \
if (output_ ## TYPE[i] != a_ ## TYPE) \
abort ()
#define DECL(TYPE) \
TYPE output_ ## TYPE[32]; \
TYPE a_ ## TYPE = (TYPE)12.2
int
main (void)
{
DECL(float);
DECL(double);
int i;
FOOD (float);
CHECKD (float);
FOOQ (float);
CHECKQ (float);
FOOD (double);
CHECKD (double);
FOOQ (double);
CHECKQ (double);
return 0;
}

65
gcc/testsuite/gcc.target/aarch64/vect-ld1r.c Normal file
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@ -0,0 +1,65 @@
/* { dg-do run } */
/* { dg-options "-O3" } */
extern void abort (void);
#include "stdint.h"
#include "vect-ld1r.x"
DEF (int8_t)
DEF (int16_t)
DEF (int32_t)
DEF (int64_t)
#define FOOD(TYPE) \
foo_ ## TYPE ## _d (&a_ ## TYPE, output_ ## TYPE)
#define FOOQ(TYPE) \
foo_ ## TYPE ## _q (&a_ ## TYPE, output_ ## TYPE)
#define CHECKD(TYPE) \
for (i = 0; i < 8 / sizeof (TYPE); i++) \
if (output_ ## TYPE[i] != a_ ## TYPE) \
abort ()
#define CHECKQ(TYPE) \
for (i = 0; i < 32 / sizeof (TYPE); i++) \
if (output_ ## TYPE[i] != a_ ## TYPE) \
abort ()
#define DECL(TYPE) \
TYPE output_ ## TYPE[32]; \
TYPE a_ ## TYPE = (TYPE)12
int
main (void)
{
DECL(int8_t);
DECL(int16_t);
DECL(int32_t);
DECL(int64_t);
int i;
FOOD (int8_t);
CHECKD (int8_t);
FOOQ (int8_t);
CHECKQ (int8_t);
FOOD (int16_t);
CHECKD (int16_t);
FOOQ (int16_t);
CHECKQ (int16_t);
FOOD (int32_t);
CHECKD (int32_t);
FOOQ (int32_t);
CHECKQ (int32_t);
FOOD (int64_t);
CHECKD (int64_t);
FOOQ (int64_t);
CHECKQ (int64_t);
return 0;
}

15
gcc/testsuite/gcc.target/aarch64/vect-ld1r.x Normal file
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@ -0,0 +1,15 @@
#define DEF(TYPE) \
void \
foo_ ## TYPE ## _d (TYPE *a, TYPE *output) \
{ \
int i; \
for (i = 0; i < 8 / sizeof (TYPE); i++) \
output[i] = *a; \
} \
foo_ ## TYPE ## _q (TYPE *a, TYPE *output) \
{ \
int i; \
for (i = 0; i < 32 / sizeof (TYPE); i++) \
output[i] = *a; \
}