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alpha.c, [...]: Follow spelling conventions.

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* config/alpha/alpha.c, config/alpha/alpha.md,
	config/alpha/lib1funcs.asm, config/alpha/vms-crt0-64.c,
	config/alpha/vms-psxcrt0-64.c, config/arc/arc.c,
	config/arc/arc.h, config/arm/arm.c, config/arm/arm.md,
	config/arm/lib1funcs.asm: Follow spelling conventions.

From-SVN: r122150
This commit is contained in:
Kazu Hirata 2007-02-20 02:10:57 +00:00 committed by Kazu Hirata
parent 10daf67706
commit a50aa82741
11 changed files with 30 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
gcc/ChangeLog
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@ -1,3 +1,11 @@
2007-02-20 Kazu Hirata <kazu@codesourcery.com>
* config/alpha/alpha.c, config/alpha/alpha.md,
config/alpha/lib1funcs.asm, config/alpha/vms-crt0-64.c,
config/alpha/vms-psxcrt0-64.c, config/arc/arc.c,
config/arc/arc.h, config/arm/arm.c, config/arm/arm.md,
config/arm/lib1funcs.asm: Follow spelling conventions.
2007-02-20 Alan Modra <amodra@bigpond.net.au>
PR target/29943

4
gcc/config/alpha/alpha.c
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@ -3343,7 +3343,7 @@ alpha_expand_unaligned_load (rtx tgt, rtx mem, HOST_WIDE_INT size,
/* We must use tgt here for the target. Alpha-vms port fails if we use
addr for the target, because addr is marked as a pointer and combine
knows that pointers are always sign-extended 32 bit values. */
knows that pointers are always sign-extended 32-bit values. */
addr = expand_binop (DImode, ior_optab, extl, exth, tgt, 1, OPTAB_WIDEN);
addr = expand_binop (DImode, ashr_optab, addr, GEN_INT (48),
addr, 1, OPTAB_WIDEN);
@ -6580,7 +6580,7 @@ alpha_expand_builtin (tree exp, rtx target,
#endif
/* Fold the builtin for the CMPBGE instruction. This is a vector comparison
with an 8 bit output vector. OPINT contains the integer operands; bit N
with an 8-bit output vector. OPINT contains the integer operands; bit N
of OP_CONST is set if OPINT[N] is valid. */
static tree

2
gcc/config/alpha/alpha.md
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@ -6568,7 +6568,7 @@
{
int ofs;
/* Fail 8 bit fields, falling back on a simple byte load. */
/* Fail 8-bit fields, falling back on a simple byte load. */
if (INTVAL (operands[2]) == 8)
FAIL;

4
gcc/config/alpha/lib1funcs.asm
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@ -200,7 +200,7 @@ FUNCTION_NAME:
#define N RETREG
#endif
/* Perform conversion from 32 bit types to 64 bit types. */
/* Perform conversion from 32-bit types to 64-bit types. */
#if SIZE == 32
#if TYPE == SIGNED
/* If there are problems with the signed case, add these instructions.
@ -303,7 +303,7 @@ $46:
#endif
/* Sign extend an *unsigned* 32 bit result, as required by the Alpha
/* Sign extend an *unsigned* 32-bit result, as required by the Alpha
conventions. */
#if TYPE == UNSIGNED && SIZE == 32
/* This could be avoided by adding some CPP hair to the divide loop.

2
gcc/config/alpha/vms-crt0-64.c
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@ -77,7 +77,7 @@ __main (arg1, arg2, arg3, image_file_desc, arg5, arg6)
#pragma __pointer_size long
/* Reallocate argv with 64 bit pointers. */
/* Reallocate argv with 64-bit pointers. */
long_argv = (char **) malloc (sizeof (char *) * (argc + 1));
for (i = 0; i < argc; i++)

2
gcc/config/alpha/vms-psxcrt0-64.c
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@ -79,7 +79,7 @@ __main (arg1, arg2, arg3, image_file_desc, arg5, arg6)
#pragma __pointer_size long
/* Reallocate argv with 64 bit pointers. */
/* Reallocate argv with 64-bit pointers. */
long_argv = (char **) malloc (sizeof (char *) * (argc + 1));
for (i = 0; i < argc; i++)

10
gcc/config/arc/arc.c
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@ -262,7 +262,7 @@ arc_select_cc_mode (enum rtx_code op,
indexed by hard register number, and one indexed by mode. */
/* The purpose of arc_mode_class is to shrink the range of modes so that
they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
mapped into one arc_mode_class mode. */
enum arc_mode_class {
@ -479,7 +479,7 @@ long_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
case CONST_INT :
return !SMALL_INT (INTVAL (op));
case CONST_DOUBLE :
/* These can happen because large unsigned 32 bit constants are
/* These can happen because large unsigned 32-bit constants are
represented this way (the multiplication patterns can cause these
to be generated). They also occur for SFmode values. */
return 1;
@ -516,7 +516,7 @@ long_immediate_loadstore_operand (rtx op,
assume that it does. */
return 1;
case CONST_DOUBLE :
/* These can happen because large unsigned 32 bit constants are
/* These can happen because large unsigned 32-bit constants are
represented this way (the multiplication patterns can cause these
to be generated). They also occur for SFmode values. */
return 1;
@ -550,10 +550,10 @@ move_src_operand (rtx op, enum machine_mode mode)
case CONST_DOUBLE :
/* We can handle DImode integer constants in SImode if the value
(signed or unsigned) will fit in 32 bits. This is needed because
large unsigned 32 bit constants are represented as CONST_DOUBLEs. */
large unsigned 32-bit constants are represented as CONST_DOUBLEs. */
if (mode == SImode)
return arc_double_limm_p (op);
/* We can handle 32 bit floating point constants. */
/* We can handle 32-bit floating point constants. */
if (mode == SFmode)
return GET_MODE (op) == SFmode;
return 0;

8
gcc/config/arc/arc.h
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@ -430,7 +430,7 @@ extern enum reg_class arc_regno_reg_class[FIRST_PSEUDO_REGISTER];
Here VALUE is the CONST_DOUBLE rtx itself. */
/* 'G' is used for integer values for the multiplication insns where the
operands are extended from 4 bytes to 8 bytes.
'H' is used when any 64 bit constant is allowed. */
'H' is used when any 64-bit constant is allowed. */
#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
((C) == 'G' ? arc_double_limm_p (VALUE) \
: (C) == 'H' ? 1 \
@ -671,7 +671,7 @@ arc_eligible_for_epilogue_delay (TRIAL, SLOTS_FILLED)
/* Output assembler code for a block containing the constant parts
of a trampoline, leaving space for the variable parts. */
/* On the ARC, the trampoline is quite simple as we have 32 bit immediate
/* On the ARC, the trampoline is quite simple as we have 32-bit immediate
constants.
mov r24,STATIC
@ -714,7 +714,7 @@ do { \
|| GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
/* Nonzero if the constant value X is a legitimate general operand.
We can handle any 32 or 64 bit constant. */
We can handle any 32- or 64-bit constant. */
/* "1" should work since the largest constant should be a 64 bit critter. */
/* ??? Not sure what to do for 64x32 compiler. */
#define LEGITIMATE_CONSTANT_P(X) 1
@ -1060,7 +1060,7 @@ do { if ((LOG) != 0) fprintf (FILE, "\t.align %d\n", 1 << (LOG)); } while (0)
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
between pointers and any other objects of this machine mode. */
/* ??? The arc doesn't have full 32 bit pointers, but making this PSImode has
/* ??? The arc doesn't have full 32-bit pointers, but making this PSImode has
its own problems (you have to add extendpsisi2 and trucnsipsi2 but how does
one do it without getting excess code?). Try to avoid it. */
#define Pmode SImode

8
gcc/config/arm/arm.c
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@ -3190,7 +3190,7 @@ current_file_function_operand (rtx sym_ref)
return 0;
}
/* Return nonzero if a 32 bit "long_call" should be generated for
/* Return nonzero if a 32-bit "long_call" should be generated for
this call. We generate a long_call if the function:
a. has an __attribute__((long call))
@ -4076,7 +4076,7 @@ thumb1_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p)
&& thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1))))
return 1;
/* REG+const has 10 bit offset for SP, but only SImode and
/* REG+const has 10-bit offset for SP, but only SImode and
larger is supported. */
/* ??? Should probably check for DI/DFmode overflow here
just like GO_IF_LEGITIMATE_OFFSET does. */
@ -4385,8 +4385,8 @@ arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode)
HOST_WIDE_INT mask, base, index;
rtx base_reg;
/* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only
use a 8 bit index. So let's use a 12 bit index for SImode only and
/* ldr and ldrb can use a 12-bit index, ldrsb and the rest can only
use a 8-bit index. So let's use a 12-bit index for SImode only and
hope that arm_gen_constant will enable ldrb to use more bits. */
bits = (mode == SImode) ? 12 : 8;
mask = (1 << bits) - 1;

2
gcc/config/arm/arm.md
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@ -8152,7 +8152,7 @@
operands[2] = const0_rtx;
/* This is to decide if we should generate indirect calls by loading the
32 bit address of the callee into a register before performing the
32-bit address of the callee into a register before performing the
branch and link. operand[2] encodes the long_call/short_call
attribute of the function being called. This attribute is set whenever
__attribute__((long_call/short_call)) or #pragma long_call/no_long_call

2
gcc/config/arm/lib1funcs.asm
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@ -444,7 +444,7 @@ pc .req r15
@ Initially shift the divisor left 3 bits if possible,
@ set curbit accordingly. This allows for curbit to be located
@ at the left end of each 4 bit nibbles in the division loop
@ at the left end of each 4-bit nibbles in the division loop
@ to save one loop in most cases.
tst \divisor, #0xe0000000
moveq \divisor, \divisor, lsl #3