[Arm] Add support for missing CPUs
This patch adds '-mcpu' options for following CPUs: Cortex-M35P, Cortex-A77, Cortex-A76AE. Related specifications are as following: https://developer.arm.com/ip-products/processors/cortex-m https://developer.arm.com/ip-products/processors/cortex-a 2019-08-23 Dennis Zhang <dennis.zhang@arm.com> * config/arm/arm-cpus.in (cortex-m35p): New entry. (cortex-a76ae): Likewise. (cortex-a77): Likewise * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. * doc/invoke.texi (ARM Options): Document cortex-m35p, cortx-a76ae, cortex-a77 CPU options. From-SVN: r274845
This commit is contained in:
Dennis Zhang
Kyrylo Tkachov
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1628b2faf0
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a50f423695
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@ -1,3 +1,13 @@
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2019-08-23 Dennis Zhang <dennis.zhang@arm.com>
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* config/arm/arm-cpus.in (cortex-m35p): New entry.
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(cortex-a76ae): Likewise.
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(cortex-a77): Likewise
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* config/arm/arm-tables.opt: Regenerate.
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* config/arm/arm-tune.md: Likewise.
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* doc/invoke.texi (ARM Options): Document cortex-m35p, cortx-a76ae,
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cortex-a77 CPU options.
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2019-08-23 Martin Liska <mliska@suse.cz>
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* profile.c (instrument_values): Do not set
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@ -1331,6 +1331,28 @@ begin cpu cortex-a76
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part d0b
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end cpu cortex-a76
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begin cpu cortex-a76ae
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cname cortexa76ae
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8.2-a+fp16+dotprod+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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vendor 41
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part d0e
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end cpu cortex-a76ae
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begin cpu cortex-a77
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cname cortexa77
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tune for cortex-a57
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tune flags LDSCHED
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architecture armv8.2-a+fp16+dotprod+simd
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option crypto add FP_ARMv8 CRYPTO
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costs cortex_a57
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vendor 41
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part d0d
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end cpu cortex-a77
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begin cpu neoverse-n1
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cname neoversen1
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alias !ares
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@ -1379,6 +1401,15 @@ begin cpu cortex-m33
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costs v7m
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end cpu cortex-m33
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begin cpu cortex-m35p
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cname cortexm35p
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tune flags LDSCHED
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architecture armv8-m.main+dsp+fp
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option nofp remove ALL_FP
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option nodsp remove armv7em
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costs v7m
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end cpu cortex-m35p
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# V8 R-profile implementations.
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begin cpu cortex-r52
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cname cortexr52
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@ -234,6 +234,12 @@ Enum(processor_type) String(cortex-a75) Value( TARGET_CPU_cortexa75)
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EnumValue
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Enum(processor_type) String(cortex-a76) Value( TARGET_CPU_cortexa76)
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EnumValue
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Enum(processor_type) String(cortex-a76ae) Value( TARGET_CPU_cortexa76ae)
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EnumValue
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Enum(processor_type) String(cortex-a77) Value( TARGET_CPU_cortexa77)
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EnumValue
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Enum(processor_type) String(neoverse-n1) Value( TARGET_CPU_neoversen1)
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@ -249,6 +255,9 @@ Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
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EnumValue
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Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
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EnumValue
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Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p)
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EnumValue
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Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
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@ -44,7 +44,8 @@
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cortexa73,exynosm1,xgene1,
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cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,
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cortexa73cortexa53,cortexa55,cortexa75,
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cortexa76,neoversen1,cortexa75cortexa55,
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cortexa76cortexa55,cortexm23,cortexm33,
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cortexa76,cortexa76ae,cortexa77,
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neoversen1,cortexa75cortexa55,cortexa76cortexa55,
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cortexm23,cortexm33,cortexm35p,
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cortexr52"
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(const (symbol_ref "((enum attr_tune) arm_tune)")))
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@ -17650,10 +17650,12 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
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@samp{cortex-a9}, @samp{cortex-a12}, @samp{cortex-a15}, @samp{cortex-a17},
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@samp{cortex-a32}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
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@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
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@samp{cortex-a76}, @samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
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@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77},
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@samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
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@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
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@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
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@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
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@samp{cortex-m35p},
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@samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply},
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@samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4},
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@samp{neoverse-n1}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2},
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@ -17717,14 +17719,14 @@ The following extension options are common to the listed CPUs:
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@table @samp
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@item +nodsp
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Disable the DSP instructions on @samp{cortex-m33}.
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Disable the DSP instructions on @samp{cortex-m33}, @samp{cortex-m35p}.
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@item +nofp
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Disables the floating-point instructions on @samp{arm9e},
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@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e},
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@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s},
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@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8},
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@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}.
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@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m33} and @samp{cortex-m35p}.
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Disables the floating-point and SIMD instructions on
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@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7},
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@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12},
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