sh.md (udivsi3_i1, [...]): Name.
* sh.md (udivsi3_i1, divsi3_i1, umulhisi3_i, mulhisi3_i): Name. (smulsi3_highpart_i): Name. (udivsi3): Wrap emitted insns in REG_LIBCALL / REG_RETVAL notes. (divsi3, mulhisi3, umulhisi3, mulsidi3, umulsidi3): Likewise. (smulsi3_highpart, umulsi3_highpart): Likewise. (mulsidi3_i, umulsidi3_i): Make rtl describe operation correctly independent of endianness. (mulsidi3, umulsidi3): Now define_insn. Hide details that confuse the optimizers. (mulsidi3+1, umulsidi3+1): New define_split. From-SVN: r31997
This commit is contained in:
J"orn Rennecke
Joern Rennecke
parent
73d7c68909
commit
a512fa978e
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@ -1,3 +1,17 @@
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Wed Feb 16 00:58:06 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
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* sh.md (udivsi3_i1, divsi3_i1, umulhisi3_i, mulhisi3_i): Name.
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(smulsi3_highpart_i): Name.
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(udivsi3): Wrap emitted insns in REG_LIBCALL / REG_RETVAL notes.
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(divsi3, mulhisi3, umulhisi3, mulsidi3, umulsidi3): Likewise.
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(smulsi3_highpart, umulsi3_highpart): Likewise.
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(mulsidi3_i, umulsidi3_i): Make rtl describe operation
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correctly independent of endianness.
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(mulsidi3, umulsidi3): Now define_insn. Hide details that
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confuse the optimizers.
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(mulsidi3+1, umulsidi3+1): New define_split.
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Tue Feb 15 23:22:26 2000 Andrew Haley <aph@cygnus.com>
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* config/sh/sh.md: Guard insn splits against illegal registers.
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@ -868,7 +868,7 @@
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;; This reload would clobber the value in r0 we are trying to store.
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;; If we let reload allocate r0, then this problem can never happen.
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(define_insn ""
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(define_insn "udivsi3_i1"
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[(set (match_operand:SI 0 "register_operand" "=z")
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(udiv:SI (reg:SI 4) (reg:SI 5)))
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(clobber (reg:SI 18))
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@ -917,9 +917,9 @@
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(set_attr "needs_delay_slot" "yes")])
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(define_expand "udivsi3"
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[(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
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[(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
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(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
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(set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
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(set (match_dup 3) (symbol_ref:SI "__udivsi3"))
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(parallel [(set (match_operand:SI 0 "register_operand" "")
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(udiv:SI (reg:SI 4)
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(reg:SI 5)))
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@ -930,22 +930,36 @@
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""
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"
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{
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rtx first, last;
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operands[3] = gen_reg_rtx(SImode);
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/* Emit the move of the address to a pseudo outside of the libcall. */
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if (TARGET_HARD_SH4)
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{
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emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
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emit_move_insn (gen_rtx (REG, SImode, 5), operands[2]);
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emit_move_insn (operands[3],
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gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
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if (TARGET_FPU_SINGLE)
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emit_insn (gen_udivsi3_i4_single (operands[0], operands[3]));
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last = gen_udivsi3_i4_single (operands[0], operands[3]);
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else
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emit_insn (gen_udivsi3_i4 (operands[0], operands[3]));
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DONE;
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last = gen_udivsi3_i4 (operands[0], operands[3]);
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}
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else
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{
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emit_move_insn (operands[3],
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gen_rtx_SYMBOL_REF (SImode, \"__udivsi3\"));
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last = gen_udivsi3_i1 (operands[0], operands[3]);
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}
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first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
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emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
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last = emit_insn (last);
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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(define_insn ""
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(define_insn "divsi3_i1"
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[(set (match_operand:SI 0 "register_operand" "=z")
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(div:SI (reg:SI 4) (reg:SI 5)))
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(clobber (reg:SI 18))
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@ -987,9 +1001,9 @@
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(set_attr "needs_delay_slot" "yes")])
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(define_expand "divsi3"
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[(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
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[(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
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(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
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(set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
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(set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
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(parallel [(set (match_operand:SI 0 "register_operand" "")
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(div:SI (reg:SI 4)
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(reg:SI 5)))
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@ -1002,26 +1016,39 @@
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""
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"
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{
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rtx first, last;
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operands[3] = gen_reg_rtx(SImode);
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/* Emit the move of the address to a pseudo outside of the libcall. */
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if (TARGET_HARD_SH4)
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{
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emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
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emit_move_insn (gen_rtx (REG, SImode, 5), operands[2]);
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emit_move_insn (operands[3],
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gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
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if (TARGET_FPU_SINGLE)
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emit_insn (gen_divsi3_i4_single (operands[0], operands[3]));
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last = gen_divsi3_i4_single (operands[0], operands[3]);
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else
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emit_insn (gen_divsi3_i4 (operands[0], operands[3]));
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DONE;
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last = gen_divsi3_i4 (operands[0], operands[3]);
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}
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else
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{
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emit_move_insn (operands[3], gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3\"));
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last = gen_divsi3_i1 (operands[0], operands[3]);
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}
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first = emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
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emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
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last = emit_insn (last);
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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;; -------------------------------------------------------------------------
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;; Multiplication instructions
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;; -------------------------------------------------------------------------
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(define_insn ""
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(define_insn "umulhisi3_i"
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[(set (reg:SI 21)
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(mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
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(zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
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@ -1029,7 +1056,7 @@
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"mulu %1,%0"
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[(set_attr "type" "smpy")])
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(define_insn ""
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(define_insn "mulhisi3_i"
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[(set (reg:SI 21)
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(mult:SI (sign_extend:SI
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(match_operand:HI 0 "arith_reg_operand" "r"))
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@ -1048,7 +1075,18 @@
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 21))]
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""
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"")
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"
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{
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rtx first, last;
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first = emit_insn (gen_mulhisi3_i (operands[1], operands[2]));
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last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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(define_expand "umulhisi3"
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[(set (reg:SI 21)
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@ -1059,7 +1097,18 @@
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 21))]
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""
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"")
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"
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{
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rtx first, last;
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first = emit_insn (gen_umulhisi3_i (operands[1], operands[2]));
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last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 21));
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
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;; a call to a routine which clobbers known registers.
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@ -1142,72 +1191,90 @@
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}")
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(define_insn "mulsidi3_i"
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[(set (reg:DI 20)
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(mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
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(const_int 32))))
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(set (reg:SI 21)
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(mult:SI (match_dup 0)
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(match_dup 1)))]
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"TARGET_SH2"
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"dmuls.l %1,%0"
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[(set_attr "type" "dmpy")])
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(define_expand "mulsidi3"
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[(set (reg:DI 20)
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(define_insn "mulsidi3"
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[(set (match_operand:DI 0 "arith_reg_operand" "=r")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
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(clobber (reg:DI 20))]
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"TARGET_SH2"
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"#")
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(define_split
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[(set (match_operand:DI 0 "arith_reg_operand" "")
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(mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(reg:DI 20))]
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(clobber (reg:DI 20))]
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"TARGET_SH2"
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[(const_int 0)]
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"
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{
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/* We must swap the two words when copying them from MACH/MACL to the
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output register. */
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if (TARGET_LITTLE_ENDIAN)
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{
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rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
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rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
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rtx low_dst = gen_lowpart (SImode, operands[0]);
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rtx high_dst = gen_highpart (SImode, operands[0]);
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emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
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emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
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emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
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emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
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emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
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DONE;
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}
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emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
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emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
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/* We need something to tag the possible REG_EQUAL notes on to. */
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}")
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(define_insn "umulsidi3_i"
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[(set (reg:DI 20)
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(mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
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(const_int 32))))
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(set (reg:SI 21)
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(mult:SI (match_dup 0)
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(match_dup 1)))]
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"TARGET_SH2"
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"dmulu.l %1,%0"
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[(set_attr "type" "dmpy")])
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(define_expand "umulsidi3"
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[(set (reg:DI 20)
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(define_insn "umulsidi3"
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[(set (match_operand:DI 0 "arith_reg_operand" "=r")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "r"))))
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(clobber (reg:DI 20))]
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"TARGET_SH2"
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"#")
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(define_split
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[(set (match_operand:DI 0 "arith_reg_operand" "")
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(mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
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(zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
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(set (match_operand:DI 0 "arith_reg_operand" "")
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(reg:DI 20))]
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(clobber (reg:DI 20))]
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"TARGET_SH2"
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[(const_int 0)]
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"
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{
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/* We must swap the two words when copying them from MACH/MACL to the
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output register. */
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if (TARGET_LITTLE_ENDIAN)
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{
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rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
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rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
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rtx low_dst = gen_lowpart (SImode, operands[0]);
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rtx high_dst = gen_highpart (SImode, operands[0]);
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emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
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emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
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emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
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emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
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emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
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DONE;
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}
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emit_move_insn (low_dst, gen_rtx_REG (SImode, 21));
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emit_move_insn (high_dst, gen_rtx_REG (SImode, 20));
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/* We need something to tag the possible REG_EQUAL notes on to. */
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emit_move_insn (operands[0], operands[0]);
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DONE;
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}")
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(define_insn ""
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(define_insn "smulsi3_highpart_i"
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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@ -1228,9 +1295,20 @@
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 20))]
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"TARGET_SH2"
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"")
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"
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{
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rtx first, last;
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(define_insn ""
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first = emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
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last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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(define_insn "umulsi3_highpart_i"
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[(set (reg:SI 20)
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(truncate:SI
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(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
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@ -1251,7 +1329,18 @@
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(set (match_operand:SI 0 "arith_reg_operand" "")
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(reg:SI 20))]
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"TARGET_SH2"
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"")
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"
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{
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rtx first, last;
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first = emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
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last = emit_move_insn (operands[0], gen_rtx_REG (SImode, 20));
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/* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
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invariant code motion can move it. */
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REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
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REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
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DONE;
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}")
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;; -------------------------------------------------------------------------
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;; Logical operations
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