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config.gcc: Support "tremont".

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2018-06-07  Olga Makhotina  <olga.makhotina@intel.com>

gcc/

        * config.gcc: Support "tremont".
        * config/i386/driver-i386.c (host_detect_local_cpu): Detect "tremont".
        * config/i386/i386-c.c (ix86_target_macros_internal): Handle
        PROCESSOR_TREMONT.
        * config/i386/i386.c (m_TREMONT): Define.
        (processor_target_table): Add "tremont".
        (PTA_TREMONT): Define.
        (ix86_lea_outperforms): Add TARGET_TREMONT.
        (get_builtin_code_for_version): Handle PROCESSOR_TREMONT.
        (fold_builtin_cpu): Add M_INTEL_TREMONT, replace M_INTEL_GOLDMONT
        and M_INTEL_GOLDMONT_PLUS.
        (fold_builtin_cpu): Add "tremont".
        (ix86_add_stmt_cost): Add TARGET_TREMONT.
        (ix86_option_override_internal): Add "tremont".
        * config/i386/i386.h (processor_costs): Define TARGET_TREMONT.
        (processor_type): Add PROCESSOR_TREMONT.
        * config/i386/x86-tune.def: Add m_TREMONT.
        * doc/invoke.texi: Add tremont as x86 -march=/-mtune= CPU type.

gcc/testsuite/

        * gcc.target/i386/funcspec-56.inc: Test arch=tremont.

libgcc/

        * config/i386/cpuinfo.h (processor_types): Add INTEL_TREMONT.

From-SVN: r261270
This commit is contained in:
Olga Makhotina 2018-06-07 11:07:05 +00:00 committed by Sebastian Peryt
parent cef87b05f2
commit a548a5a1d6
12 changed files with 92 additions and 30 deletions
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21
gcc/ChangeLog
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@ -1,3 +1,24 @@
2018-06-07 Olga Makhotina <olga.makhotina@intel.com>
* config.gcc: Support "tremont".
* config/i386/driver-i386.c (host_detect_local_cpu): Detect "tremont".
* config/i386/i386-c.c (ix86_target_macros_internal): Handle
PROCESSOR_TREMONT.
* config/i386/i386.c (m_TREMONT): Define.
(processor_target_table): Add "tremont".
(PTA_TREMONT): Define.
(ix86_lea_outperforms): Add TARGET_TREMONT.
(get_builtin_code_for_version): Handle PROCESSOR_TREMONT.
(fold_builtin_cpu): Add M_INTEL_TREMONT, replace M_INTEL_GOLDMONT
and M_INTEL_GOLDMONT_PLUS.
(fold_builtin_cpu): Add "tremont".
(ix86_add_stmt_cost): Add TARGET_TREMONT.
(ix86_option_override_internal): Add "tremont".
* config/i386/i386.h (processor_costs): Define TARGET_TREMONT.
(processor_type): Add PROCESSOR_TREMONT.
* config/i386/x86-tune.def: Add m_TREMONT.
* doc/invoke.texi: Add tremont as x86 -march=/-mtune= CPU type.
2018-06-07 Jozef Lawrynowicz <jozef.l@mittosystems.com>
* gcc/config/msp430/msp430.c (msp430_mcu_name): Set the "i" in the

2
gcc/config.gcc
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@ -650,7 +650,7 @@ bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
skylake-avx512 cannonlake icelake-client icelake-server skylake goldmont \
goldmont-plus x86-64 native"
goldmont-plus tremont x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.

5
gcc/config/i386/driver-i386.c
View File

@ -872,7 +872,10 @@ const char *host_detect_local_cpu (int argc, const char **argv)
cpu = "sandybridge";
else if (has_sse4_2)
{
if (has_sgx)
if (has_gfni)
/* Assume Tremont. */
cpu = "tremont";
else if (has_sgx)
/* Assume Goldmont Plus. */
cpu = "goldmont-plus";
else if (has_xsave)

7
gcc/config/i386/i386-c.c
View File

@ -182,6 +182,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__goldmont_plus");
def_or_undef (parse_in, "__goldmont_plus__");
break;
case PROCESSOR_TREMONT:
def_or_undef (parse_in, "__tremont");
def_or_undef (parse_in, "__tremont__");
break;
case PROCESSOR_KNL:
def_or_undef (parse_in, "__knl");
def_or_undef (parse_in, "__knl__");
@ -325,6 +329,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_GOLDMONT_PLUS:
def_or_undef (parse_in, "__tune_goldmont_plus__");
break;
case PROCESSOR_TREMONT:
def_or_undef (parse_in, "__tune_tremont__");
break;
case PROCESSOR_KNL:
def_or_undef (parse_in, "__tune_knl__");
break;

21
gcc/config/i386/i386.c
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@ -152,6 +152,7 @@ const struct processor_costs *ix86_cost = NULL;
#define m_ICELAKE_SERVER (HOST_WIDE_INT_1U<<PROCESSOR_ICELAKE_SERVER)
#define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
#define m_GOLDMONT_PLUS (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS)
#define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT)
#define m_INTEL (HOST_WIDE_INT_1U<<PROCESSOR_INTEL)
#define m_GEODE (HOST_WIDE_INT_1U<<PROCESSOR_GEODE)
@ -863,6 +864,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{"silvermont", &slm_cost, 16, 15, 16, 7, 16},
{"goldmont", &slm_cost, 16, 15, 16, 7, 16},
{"goldmont-plus", &slm_cost, 16, 15, 16, 7, 16},
{"tremont", &slm_cost, 16, 15, 16, 7, 16},
{"knl", &slm_cost, 16, 15, 16, 7, 16},
{"knm", &slm_cost, 16, 15, 16, 7, 16},
{"skylake", &skylake_cost, 16, 10, 16, 10, 16},
@ -3497,6 +3499,8 @@ ix86_option_override_internal (bool main_args_p,
| PTA_FSGSBASE;
const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
| PTA_SGX;
const wide_int_bitmask PTA_TREMONT = PTA_GOLDMONT_PLUS | PTA_CLWB
| PTA_GFNI;
const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
| PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
@ -3574,6 +3578,7 @@ ix86_option_override_internal (bool main_args_p,
{"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
{"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
{"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
{"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
{"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
{"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
{"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
@ -21252,7 +21257,7 @@ ix86_lea_outperforms (rtx_insn *insn, unsigned int regno0, unsigned int regno1,
non-destructive destination purposes, or due to wanting
ability to use SCALE, the use of LEA is justified. */
if (TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS
|| TARGET_INTEL)
|| TARGET_TREMONT || TARGET_INTEL)
{
if (has_scale)
return true;
@ -32435,6 +32440,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
arg_str = "goldmont-plus";
priority = P_PROC_SSE4_2;
break;
case PROCESSOR_TREMONT:
arg_str = "tremont";
priority = P_PROC_SSE4_2;
break;
case PROCESSOR_AMDFAM10:
arg_str = "amdfam10h";
priority = P_PROC_SSE4_A;
@ -33120,6 +33129,9 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_AMD_BTVER2,
M_AMDFAM17H,
M_INTEL_KNM,
M_INTEL_GOLDMONT,
M_INTEL_GOLDMONT_PLUS,
M_INTEL_TREMONT,
M_CPU_SUBTYPE_START,
M_INTEL_COREI7_NEHALEM,
M_INTEL_COREI7_WESTMERE,
@ -33139,9 +33151,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_INTEL_COREI7_SKYLAKE_AVX512,
M_INTEL_COREI7_CANNONLAKE,
M_INTEL_COREI7_ICELAKE_CLIENT,
M_INTEL_COREI7_ICELAKE_SERVER,
M_INTEL_GOLDMONT,
M_INTEL_GOLDMONT_PLUS
M_INTEL_COREI7_ICELAKE_SERVER
};
static struct _arch_names_table
@ -33172,6 +33182,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"silvermont", M_INTEL_SILVERMONT},
{"goldmont", M_INTEL_GOLDMONT},
{"goldmont-plus", M_INTEL_GOLDMONT_PLUS},
{"tremont", M_INTEL_TREMONT},
{"knl", M_INTEL_KNL},
{"knm", M_INTEL_KNM},
{"amdfam10h", M_AMDFAM10H},
@ -51300,7 +51311,7 @@ ix86_add_stmt_cost (void *data, int count, enum vect_cost_for_stmt kind,
for Silvermont as it has out of order integer pipeline and can execute
2 scalar instruction per tick, but has in order SIMD pipeline. */
if ((TARGET_SILVERMONT || TARGET_GOLDMONT || TARGET_GOLDMONT_PLUS
|| TARGET_INTEL) && stmt_info && stmt_info->stmt)
|| TARGET_TREMONT || TARGET_INTEL) && stmt_info && stmt_info->stmt)
{
tree lhs_op = gimple_get_lhs (stmt_info->stmt);
if (lhs_op && TREE_CODE (TREE_TYPE (lhs_op)) == INTEGER_TYPE)

2
gcc/config/i386/i386.h
View File

@ -391,6 +391,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_SILVERMONT (ix86_tune == PROCESSOR_SILVERMONT)
#define TARGET_GOLDMONT (ix86_tune == PROCESSOR_GOLDMONT)
#define TARGET_GOLDMONT_PLUS (ix86_tune == PROCESSOR_GOLDMONT_PLUS)
#define TARGET_TREMONT (ix86_tune == PROCESSOR_TREMONT)
#define TARGET_KNL (ix86_tune == PROCESSOR_KNL)
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
#define TARGET_SKYLAKE (ix86_tune == PROCESSOR_SKYLAKE)
@ -2287,6 +2288,7 @@ enum processor_type
PROCESSOR_SILVERMONT,
PROCESSOR_GOLDMONT,
PROCESSOR_GOLDMONT_PLUS,
PROCESSOR_TREMONT,
PROCESSOR_KNL,
PROCESSOR_KNM,
PROCESSOR_SKYLAKE,

49
gcc/config/i386/x86-tune.def
View File

@ -42,7 +42,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_INTEL | m_KNL | m_KNM | m_K6_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
| m_GOLDMONT_PLUS | m_GENERIC)
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
on modern chips. Preffer stores affecting whole integer register
@ -51,7 +51,8 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
| m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC)
| m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_TREMONT
| m_GENERIC)
/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
destinations to be 128bit to allow register renaming on 128bit SSE units,
@ -87,14 +88,14 @@ DEF_TUNE (X86_TUNE_MOVX, "movx",
m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_KNL | m_KNM | m_INTEL
| m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512
| m_HASWELL | m_GENERIC)
| m_HASWELL | m_TREMONT | m_GENERIC)
/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
full sized loads. */
DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
| m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE
| m_GENERIC)
| m_TREMONT | m_GENERIC)
/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
conditional jump instruction for 32 bit TARGET. */
@ -133,7 +134,7 @@ DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
| m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8)
| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ATHLON_K8)
/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
considered on critical path. */
@ -195,7 +196,8 @@ DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
than 4 branch instructions in the 16 byte window. */
DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM
| m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL | m_ATHLON_K8
| m_AMDFAM10)
/*****************************************************************************/
/* Integer instruction selection tuning */
@ -224,24 +226,24 @@ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
| m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GOLDMONT
| m_GOLDMONT_PLUS | m_GENERIC))
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
for DFmode copies */
DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_KNM | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_GOLDMONT
| m_GOLDMONT_PLUS | m_GENERIC))
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
will impact LEA instruction selection. */
DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_KNL
| m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
| m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
| m_KNM)
m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
| m_KNL | m_KNM)
/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
vector path on AMD machines.
@ -259,7 +261,7 @@ DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
a conditional move. */
DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_KNL
| m_KNM | m_INTEL)
| m_KNM | m_TREMONT | m_INTEL)
/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
@ -278,18 +280,19 @@ DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER
| m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GOLDMONT_PLUS | m_GENERIC)
| m_BTVER | m_ZNVER1 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
| m_GENERIC)
/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
| m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS))
| m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT))
/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL
| m_LAKEMONT | m_AMD_MULTIPLE | m_GOLDMONT | m_GOLDMONT_PLUS
| m_GENERIC)
| m_TREMONT | m_GENERIC)
/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
for bit-manipulation instructions. */
@ -306,7 +309,7 @@ DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
if-converted sequence to one. */
DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT
| m_GOLDMONT_PLUS | m_GENERIC)
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
/*****************************************************************************/
/* 387 instruction selection tuning */
@ -323,7 +326,7 @@ DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
| m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE
| m_GOLDMONT | m_GOLDMONT_PLUS | m_GENERIC))
| m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC))
/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
@ -332,7 +335,7 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE)
DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
| m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_GOLDMONT
| m_GOLDMONT_PLUS | m_GENERIC)
| m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC)
/*****************************************************************************/
/* SSE instruction selection tuning */
@ -348,14 +351,14 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_GOLDMONT_PLUS
| m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC)
| m_TREMONT | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER1 | m_GENERIC)
/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead
of a sequence loading registers by parts. */
DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
m_NEHALEM | m_SANDYBRIDGE | m_HASWELL | m_SILVERMONT | m_KNL | m_KNM
| m_INTEL | m_SKYLAKE_AVX512 | m_GOLDMONT | m_GOLDMONT_PLUS
| m_BDVER | m_ZNVER1 | m_GENERIC)
| m_TREMONT | m_BDVER | m_ZNVER1 | m_GENERIC)
/* Use packed single precision instructions where posisble. I.e. movups instead
of movupd. */
@ -393,7 +396,7 @@ DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
fp converts to destination register. */
DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT | m_GOLDMONT_PLUS
| m_INTEL)
| m_TREMONT | m_INTEL)
/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
from FP to FP. This form of instructions avoids partial write to the
@ -408,11 +411,11 @@ DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_GOLDMONT
| m_GOLDMONT_PLUS | m_INTEL)
| m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_INTEL)
/* X86_TUNE_USE_GATHER: Use gather instructions. */
DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather",

5
gcc/doc/invoke.texi
View File

@ -26660,6 +26660,11 @@ Intel Goldmont Plus CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE,
PTWRITE, RDPID, SGX and UMIP instruction set support.
@item tremont
Intel Tremont CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
SSE4.1, SSE4.2, POPCNT, AES, PCLMUL, RDRND, XSAVE, XSAVEOPT, FSGSBASE, PTWRITE,
RDPID, SGX, UMIP, GFNI-SSE, CLWB and ENCLV instruction set support.
@item knl
Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,

4
gcc/testsuite/ChangeLog
View File

@ -1,3 +1,7 @@
2018-06-07 Olga Makhotina <olga.makhotina@intel.com>
* gcc.target/i386/funcspec-56.inc: Test arch=tremont.
2018-06-07 Jakub Jelinek <jakub@redhat.com>
PR tree-optimization/69615

1
gcc/testsuite/gcc.target/i386/funcspec-56.inc
View File

@ -144,6 +144,7 @@ extern void test_arch_core_avx2 (void) __attribute__((__target__("arch=core-avx
extern void test_arch_silvermont (void) __attribute__((__target__("arch=silvermont")));
extern void test_arch_goldmont (void) __attribute__((__target__("arch=goldmont")));
extern void test_arch_goldmont_plus (void) __attribute__((__target__("arch=goldmont-plus")));
extern void test_arch_tremont (void) __attribute__((__target__("arch=tremont")));
extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
extern void test_arch_skylake (void) __attribute__((__target__("arch=skylake")));

4
libgcc/ChangeLog
View File

@ -1,3 +1,7 @@
2018-06-07 Olga Makhotina <olga.makhotina@intel.com>
* config/i386/cpuinfo.h (processor_types): Add INTEL_TREMONT.
2018-06-07 Martin Liska <mliska@suse.cz>
* libgcov-driver.c: Rename cs_all to all and assign it from

1
libgcc/config/i386/cpuinfo.h
View File

@ -50,6 +50,7 @@ enum processor_types
INTEL_KNM,
INTEL_GOLDMONT,
INTEL_GOLDMONT_PLUS,
INTEL_TREMONT,
CPU_TYPE_MAX
};